Presentation by Bapi Vinnakota, Netronome

1. Consume. Collaborate. Contribute.Consume. Collaborate. Contribute.
ODSA PoC: Network Flow Processor
Overview
ODSA Project Workshop
March 28, 2019

2. Consume. Collaborate. Contribute.
Proposed NFP Device/Die for PoC

3. Consume. Collaborate. Contribute.
NFP Silicon: Purpose-built for Network Acceleration
Hardware Accelerators
Hardware accelerators perform compute
intensive functions such as hashing, crypto,
CAM, atomic and other functions
High Performance Distributed Mesh Fabric
Delivers multi-terabit bi-sectional bandwidth
between processing elements.
Avoids bus contention and saturation issues
Memory Engines
Multi-threaded memory engines and banks
of SRAM tightly coupled with atomic and other
hardware accelerator functions
Optimal multi-threading between Processing Cores,
H/W Accelerators and Memory Banks
Highest Multi-threading Silicon Architecture
Processing Cores
Datapath implementations (OVS, etc.)
Extensible using P4 and C Multi-threaded
processor core.
Concurrent IO operations

4. Consume. Collaborate. Contribute.
Extend Netronome Switch Fabric
• All our devices are built from Logic Blocks (or
“Islands”)
• Each Logic Block is implemented as a complete chip
• Many Terabit Switch Fabric interconnect the Logic
Blocks
• Multiple configurations, devices can be built quickly
• Minimizes engineering resources
4
FPC CPU
Net
I/F
Instruction-Driven Switch Fabric (ISF)
For async memory traffic
Firmware infrastructure for:
accelerator use, host integration
Bunch of Wires (BoW)
Link layer
Logic Blocks
PHY
Link
Memory
Management
Application
HW
Accel
…Host
I/F