An ada boost based face detection system using parallel configurable architecture with optimized computation

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AN ADABOOST-BASED FACE DETECTION SYSTEM USING PARALLEL
CONFIGURABLE ARCHITECTURE WITH OPTIMIZED COMPUTATION
By
A
PROJECT REPORT
Submitted to the Department of electronics &communication Engineering in the
FACULTY OF ENGINEERING & TECHNOLOGY
In partial fulfillment of the requirements for the award of the degree
Of
MASTER OF TECHNOLOGY
IN
ELECTRONICS &COMMUNICATION ENGINEERING
APRIL 2016

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CERTIFICATE
Certified that this project report titled “An AdaBoost-Based Face Detection System Using
Parallel Configurable Architecture With Optimized Computation” is the bonafide work of
Mr. _____________Who carried out the research under my supervision Certified further, that to
the best of my knowledge the work reported herein does not form part of any other project report
or dissertation on the basis of which a degree or award was conferred on an earlier occasion on
this or any other candidate.
Signature of the Guide Signature of the H.O.D
Name Name

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DECLARATION
I hereby declare that the project work entitled “An AdaBoost-Based Face Detection System
Using Parallel Configurable Architecture With Optimized Computation” Submitted to
BHARATHIDASAN UNIVERSITY in partial fulfillment of the requirement for the award of the
Degree of MASTER OF APPLIED ELECTRONICS is a record of original work done by me the
guidance of Prof.A.Vinayagam M.Sc., M.Phil., M.E., to the best of my knowledge, the work
reported here is not a part of any other thesis or work on the basis of which a degree or award was
conferred on an earlier occasion to me or any other candidate.
(Student Name)
(Reg.No)
Place:
Date:

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ACKNOWLEDGEMENT
I am extremely glad to present my project “An AdaBoost-Based Face Detection System Using
Parallel Configurable Architecture With Optimized Computation” which is a part of my
curriculum of third semester Master of Science in Computer science. I take this opportunity to
express my sincere gratitude to those who helped me in bringing out this project work.
I would like to express my Director,Dr. K. ANANDAN, M.A.(Eco.), M.Ed., M.Phil.,(Edn.),
PGDCA., CGT., M.A.(Psy.)of who had given me an opportunity to undertake this project.
I am highly indebted to Co-OrdinatorProf. Muniappan Department of Physics and thank from
my deep heart for her valuable comments I received through my project.
I wish to express my deep sense of gratitude to my guide
Prof. A.Vinayagam M.Sc., M.Phil., M.E., for her immense help and encouragement for
successful completion of this project.
I also express my sincere thanks to the all the staff members of Computer science for their kind
advice.
And last, but not the least, I express my deep gratitude to my parents and friends for their
encouragement and support throughout the project.

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ABSTRACT:
With the development of image sensor technology, the AdaBoost-based face detections are
widely used in many monitoring sensor networks and mobile-camera-based applications. Fast face
detection with high detection accuracy and low power consumption in such kinds of applications
is very important. Since the AdaBoost-based face detection exhibits characteristics of data
computation in dual direction and data diversity, we propose an AdaBoost-based face detection
system using parallel configurable architecture with optimized computation. The architecture
consists of parallel configurable arrays and two-level shared memory systems. It achieves dual-
direction-based integral image computation that improves parallel processing efficiency and
enables the subwindow adaptive cascade classification for data diversity, which further improves
the detection efficiency in diverse face detection. Compared with the state-of-the-art works, this
work achieves maximal performance of 30 frames/s at 1080p detection speed and extreme low
power consumption.

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INTRODUCTION:
Cyber, physical, and social computing (CPSCom) systems are integrating all kinds of
everyday life devices into heterogeneous network environments in order to ubiquitously extend
today’s various networks to monitor, interact, communicate, and control objects related to humans
and thus intelligently serve human beings. CPSCom encompasses a holistic treatment of data,
information, and knowledge from the cyber– physical–social worlds to integrate, correlate,
interpret, and provide contextually relevant abstractions to humans. The CPSCom systems are
viewed as the next phase of computing systems, building on current progress in cyber–physical
systems, sociotechnical systems, and cyber–social systems to support the computing for human
experience .
However, one of the challenges the cyber, physical, and social computing facing is how to
understand the data collected by all kinds of networks and make a decision to serve human better.
This is an application level topic mainly about pattern recognition and data mining based on
physical systems. One of the most important technologies is face detection, which is essential to
identify people. It can be widely used in smart surveillance, human–computer interaction, and all
kinds of consumer electronics. Since the AdaBoost algorithm exhibits high performance in the
detection speed and accuracy in many practical applications, the AdaBoost-based face detection is
one of the best face detection technology and has been widely used ,However, for the image sensor
network or mobilecamera-based applications, the face detections with high processing speed and
low power consumption, are required. In this work, we focus on these requirements and design
higher efficient hardware architecture for AdaBoost-based face detection
The original AdaBoost-based face detection algorithm,mainly includes integral and
squared integral image computation and cascade classification. The integral image computation,
including squared integral image computation, is both computation intensive and memory
accessing intensive and exhibits the feature of data computation in dual direction. Dual direction
here denotes the row and column directions that the accumulation operations are implemented.
Improving the efficiency of integral image computation is very important to enhance the overall
performance. Cascade classification is sensitive to the image contents. In different detection
scenes, the detection exhibits data diversity in the image contents such as image size, distance of
the face targets, and the number of face targets. The data diversity results in redundant data and
brings useless computations caused by many false candidate face regions. The data diversity

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requires the hardware to have the computation flexibility to reduce the useless computations
according to the image contents. Current studies focusing on the integral image computation and
cascade classification lack the considerations mentioned earlier. We divide the current
implementations of AdaBoost-based face detection system into three categories, which are
introduced in the following discussion.
First, many works optimize the algorithm on general-purpose architectures. These general-
purpose architectures have the computation flexibility because they are programmable. However,
the sequential instruction execution and frequent memory accessing limit the efficiency of integral
image computation. Since the algorithm is characterized by huge amounts of computation,
exploiting the parallelism of the algorithm by using multicore- or multiprocessor-based hardware
architectures, including the General Public Utilities, is an effective way to improve the processing
capability.
However, the power consumption of these works is large, which makes them lack the
adaptability in diverse detection scenes. Second, in order to achieve real-time detections, some
works implemented application-specified integrated circuits (ASICs), These works achieve fast
computation on the integral image by ASIC implementations, but the fixed circuits make it lack
the flexibility of cascade classification for data diversity. Kyrkou and Theocharides,proposed a
flexible parallel architecture based on the systolic array to improve the processing efficiency of
integral image computation. This architecture can be used in several different applications by
training different classifiers; however, its integral image is computed only in one direction, and it
lacks the design considerations for data diversity.
Third, the flexible hardware such as a field-programmable gate array (FPGA) has also been
used to process the detection algorithm , The FPGA can be reconfigured to accelerate the algorithm
and adjust the parameters to achieve the computation flexibility on the detection accuracy and
computation time. However, these FPGAs are fine-grained and statically reconfigurable, which
bring the extra power consumption and limit the processing efficiency. The integral image
computation is the key part in the algorithm and exhibits dual-direction computation; meanwhile,
the cascade classification exhibits the flexibility requirements for data diversity. The contributions
of our work can be concluded in three aspects. First, we propose the dual-direction-based integral
image computation. It can improve the parallel processing efficiency of the integral image
computation. Second, we propose the subwindow adaptive classification mechanism. Based on

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history parameters of subwindows, we predict the new parameters for the current frame to reduce
the redundant data and useless computations. Finally, we propose a parallel flexible architecture
based on these methods. The experimental results show that this architecture can achieve high
processing speed and low power consumption in the AdaBoost-based face detection. It also shows
strong computation flexibility in diverse face detections.

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CONCLUSION:
In this work, in order to achieve high processing speed and low power consumption in the
AdaBoost-based face detection, we exploited the characteristics of data computation in the
algorithm and proposed the methods of dual-direction-based integral image computation and
subwindow adaptive classification for hardware design. A parallel flexible architecture based on
these methods is proposed. Experimental results show that this architecture greatly improves the
processing speed and reduces the power consumption for face detection. Since there are many
other kinds of face detection algorithms to enhance the detection performance, the reconfigurable
property of different face detection algorithms will be investigated, and the flexibility of
architecture will be improved further.

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An ada boost based face detection system using parallel configurable architecture with optimized computation