1. Analysis of flicker noise degradation mechanism in ultra-thin oxide CMOS Student: H. C. Chang Advisor: Tahui Wang National Chiao Tung University Institute of electronics EVDTL

5. Flicker Noise Unified Model I-V model:

6. Flicker Noise Unified Model Drain current noise power: Input referred noise power:

14. Two-region model High Vt region dominate V t L 2 L 1 Q 2 Q 1

15. Extended to Three-region High Vt region dominate V t L 2 L 1 Q 2 Q 1 L 3 Q 3

18. NMOS: Cross Point in V G dependence

19. NMOS: Channel Length Dependence Low Vg High Vg after stress: at low gate bias  L independence at high gate bias  1/L

20. NMOS: V t Dependence At low gate bias  1/f noise At high gate bias  1/f noise

21. PMOS: Gate Voltage Dependence

23. PMOS: V t Dependence PMOS  1/f noise

25. Tunneling current effect on NMOS

27. Comparison of SBD effect between NMOS & PMOS

30. Oxide charge distribution

33. Two-region model along the gate width For large gate width  current bypass the SBD spot  negligible noise degradation