SlideShare ist ein Scribd-Unternehmen logo
1 von 16
Chapter:9
Dot-Matrix Display Design Using
FPGA
By:
Hossam Hassan
PhD Student, MSIS Lab,
Chungbuk National University
MSIS
Objectives
• In this lab we will deal with the dot-matrix display which used
to display information on many devices requiring a simple display
device with limited resolution.
• We will write Verilog code to simulate how to drive dot-matrix
display then synthesis the code to run on FPGA board.
Introduction
• Internally, the LEDs are organized in a matrix.
• Here's a 5x7 display internal wiring.
• Dot Matrix has two types:
• Common Cathode Type:
• a common anode for LEDs in a row - all of the anodes in
each row is common
• Common Anode Type:
• a common cathode for LEDs in a row – all the cathodes in
each row is common.
Theory of LED dot matrix display
• In a dot matrix display, multiple LEDs are wired together in rows and columns. This is done to
minimize the number of pins required to drive them.
• For example, a 5×7 matrix of LEDs (shown below) would need 35 I/O pins. By wiring all the anodes
together in rows (R1 through R7), and cathodes in columns (C1 through C5), the required number
of I/O pins is reduced to 16. Each LED is addressed by its row and column number. In the figure
below, if R4 is pulled high and C3 is pulled low, the LED in fourth row and third column will be
tuned on. Characters can be displayed by fast scanning of either rows or columns.
Common Anode
Theory of LED dot matrix display
• Suppose, we want to display the alphabet A.
• We will first select the column C1 (which means C1 is pulled low in
this case), and deselect other columns by blocking their ground paths
(one way of doing that is by pulling C2 through C5 pins to logic high).
• Now, the first column is active, and you need to turn on the LEDs in
the rows R2 through R7 of this column, which can be done by
applying forward bias voltages to these rows.
• Next, select the column C2 (and deselect all other columns), and
apply forward bias to R1 and R5, and so on.
• Therefore, by scanning across the column quickly (> 100 times per
second), and turning on the respective LEDs in each row of that
column, the persistence of vision comes in to play, and we perceive
the display image as still.
Common Anode
Theory of LED dot matrix display
• The table below gives the logic levels to be applied to R1 through R7 for each of the columns in
order to display the alphabet ‘A’.
Verilog implementation
• To run our code we have 4 Inputs and 5 Outputs.
• First, there are RESET and Clock can be entered by default in the FPGA,
• the KEY and Mode_Switch as an input to select Mode are needed to control the Dot-Matrix (same as previous labs
).
• Finally, the Dot-Matrix is used for the output.
• (LEDs and 7-Segments used same as the previous labs).
• Top Module of the Dot-Matrix example indicated the Input/Output Ports:
2 Dot-Matrix Display
Verilog implementation: Inputs/Outputs
Inputs Outputs
Verilog implementation: dot.v
Dot Matrix
Registers Declaration
Clock Division
Dot Matrix of Control Related COL Counter
Related Data Counter to be displayed on Dot Matrix
Verilog implementation: dot.v
Dot Matrix COL, RAW Data Processing
Dot Matrix COL, RAW Data Print
Verilog implementation: top.ucf
Verilog Behavioral Simulation
• To test the operation of the dot-matrix and the functionality of our
code we have to run behavioral simulation as following steps:
• Define the IOs for the Design Under Test (DUT) to provide inputs and
see the expected output on the ISim waveform.
• We define the input in the testbench as register type, so we can
provide our inputs for test.
Test bench source code
-Registers and Wires Declarations to indicate the IOs:
-Instantiate the Unit Under Test (UUT):
-Clock Generation:
Test bench source code
-Initialize our test cases:
Screen Shot of the running simulation
Homework
• Do the following exercise and explain your Verilog code with
simulation, and test on the FPGA.
• Run the Dot-Matrix Project and display the same numbers using 7-
Segments and Dot-Matrix.
• Run the Dot-Matrix Project and display different shapes.
• Run the Dot-Matrix Project and display your name moving character
by character. (Challenge)
An LED matrix display scanning
by rows to make the letter W

Weitere ähnliche Inhalte

Was ist angesagt?

An application of 8085 register interfacing with LED
An application  of 8085 register interfacing with LEDAn application  of 8085 register interfacing with LED
An application of 8085 register interfacing with LEDTaha Malampatti
 
Analysis sequential circuits
Analysis sequential circuitsAnalysis sequential circuits
Analysis sequential circuitsG Subramaniamg
 
Analog To Digital Conversion (ADC) Programming in LPC2148
Analog To Digital Conversion (ADC) Programming in LPC2148Analog To Digital Conversion (ADC) Programming in LPC2148
Analog To Digital Conversion (ADC) Programming in LPC2148Omkar Rane
 
Andes building a secure platform with the enhanced iopmp
Andes building a secure platform with the enhanced iopmpAndes building a secure platform with the enhanced iopmp
Andes building a secure platform with the enhanced iopmpRISC-V International
 
Making Of 0-9 Decade Counter with 7 segment display
Making Of 0-9 Decade Counter with 7 segment displayMaking Of 0-9 Decade Counter with 7 segment display
Making Of 0-9 Decade Counter with 7 segment displayOmkar Rane
 
Coal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly ProgrammingCoal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly ProgrammingMuhammad Taqi Hassan Bukhari
 
Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...
Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...
Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...Vincent Claes
 
System verilog control flow
System verilog control flowSystem verilog control flow
System verilog control flowPushpa Yakkala
 
Verilog hdl design examples
Verilog hdl design examplesVerilog hdl design examples
Verilog hdl design examplesdennis gookyi
 
Verilog Tasks & Functions
Verilog Tasks & FunctionsVerilog Tasks & Functions
Verilog Tasks & Functionsanand hd
 
Programmable peripheral interface 8255
Programmable peripheral interface 8255Programmable peripheral interface 8255
Programmable peripheral interface 8255Marajulislam3
 

Was ist angesagt? (20)

Uvm dac2011 final_color
Uvm dac2011 final_colorUvm dac2011 final_color
Uvm dac2011 final_color
 
An application of 8085 register interfacing with LED
An application  of 8085 register interfacing with LEDAn application  of 8085 register interfacing with LED
An application of 8085 register interfacing with LED
 
Analysis sequential circuits
Analysis sequential circuitsAnalysis sequential circuits
Analysis sequential circuits
 
Ec8791 lpc2148 pwm
Ec8791 lpc2148 pwmEc8791 lpc2148 pwm
Ec8791 lpc2148 pwm
 
1.ppi 8255
1.ppi 8255 1.ppi 8255
1.ppi 8255
 
Analog To Digital Conversion (ADC) Programming in LPC2148
Analog To Digital Conversion (ADC) Programming in LPC2148Analog To Digital Conversion (ADC) Programming in LPC2148
Analog To Digital Conversion (ADC) Programming in LPC2148
 
Andes building a secure platform with the enhanced iopmp
Andes building a secure platform with the enhanced iopmpAndes building a secure platform with the enhanced iopmp
Andes building a secure platform with the enhanced iopmp
 
Making Of 0-9 Decade Counter with 7 segment display
Making Of 0-9 Decade Counter with 7 segment displayMaking Of 0-9 Decade Counter with 7 segment display
Making Of 0-9 Decade Counter with 7 segment display
 
Verilog lab manual (ECAD and VLSI Lab)
Verilog lab manual (ECAD and VLSI Lab)Verilog lab manual (ECAD and VLSI Lab)
Verilog lab manual (ECAD and VLSI Lab)
 
Advance Peripheral Bus
Advance Peripheral Bus Advance Peripheral Bus
Advance Peripheral Bus
 
Verilog HDL
Verilog HDLVerilog HDL
Verilog HDL
 
Coal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly ProgrammingCoal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly Programming
 
Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...
Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...
Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedde...
 
System verilog control flow
System verilog control flowSystem verilog control flow
System verilog control flow
 
Verilog hdl design examples
Verilog hdl design examplesVerilog hdl design examples
Verilog hdl design examples
 
Ovm vs-uvm
Ovm vs-uvmOvm vs-uvm
Ovm vs-uvm
 
Verilog Tasks & Functions
Verilog Tasks & FunctionsVerilog Tasks & Functions
Verilog Tasks & Functions
 
Interfacing of LCD with LPC2148
Interfacing of LCD with LPC2148Interfacing of LCD with LPC2148
Interfacing of LCD with LPC2148
 
Programmable peripheral interface 8255
Programmable peripheral interface 8255Programmable peripheral interface 8255
Programmable peripheral interface 8255
 
4 bit Binary counter
4 bit Binary counter4 bit Binary counter
4 bit Binary counter
 

Ähnlich wie Dot matrix display design using fpga

Dot matrix module interface wit Raspberry Pi
Dot matrix module interface wit Raspberry PiDot matrix module interface wit Raspberry Pi
Dot matrix module interface wit Raspberry Pianishgoel
 
PRESENTATION ON DATA STRUCTURE AND THEIR TYPE
PRESENTATION ON DATA STRUCTURE AND THEIR TYPEPRESENTATION ON DATA STRUCTURE AND THEIR TYPE
PRESENTATION ON DATA STRUCTURE AND THEIR TYPEnikhilcse1
 
456589.-Compiler-Design-Code-Generation (1).ppt
456589.-Compiler-Design-Code-Generation (1).ppt456589.-Compiler-Design-Code-Generation (1).ppt
456589.-Compiler-Design-Code-Generation (1).pptMohibKhan79
 
Varsha patil AISSMS IOIT Pune mca te pu book
Varsha patil AISSMS IOIT Pune mca te pu bookVarsha patil AISSMS IOIT Pune mca te pu book
Varsha patil AISSMS IOIT Pune mca te pu bookVarsha Patil
 
5th unit Microprocessor 8085
5th unit Microprocessor 80855th unit Microprocessor 8085
5th unit Microprocessor 8085Mani Afranzio
 
arduinoworkshop-160204051621.pdf
arduinoworkshop-160204051621.pdfarduinoworkshop-160204051621.pdf
arduinoworkshop-160204051621.pdfAbdErrezakChahoub
 
Industrial training report of embedded system and robotics
Industrial training report of embedded system and roboticsIndustrial training report of embedded system and robotics
Industrial training report of embedded system and roboticsPallavi Bharti
 
Circuitrix@Pragyan 2015 NITT
Circuitrix@Pragyan 2015 NITTCircuitrix@Pragyan 2015 NITT
Circuitrix@Pragyan 2015 NITTSrivignessh Pss
 
L3-.pptx
L3-.pptxL3-.pptx
L3-.pptxasdq4
 
FPGA design with CλaSH
FPGA design with CλaSHFPGA design with CλaSH
FPGA design with CλaSHConrad Parker
 
CLC and SLC with examples.pptx
CLC and SLC with examples.pptxCLC and SLC with examples.pptx
CLC and SLC with examples.pptxAhmedLakhwera
 
14-Bill-Tiffany-SigmaSense-VF2023.pdf
14-Bill-Tiffany-SigmaSense-VF2023.pdf14-Bill-Tiffany-SigmaSense-VF2023.pdf
14-Bill-Tiffany-SigmaSense-VF2023.pdfSamHoney6
 
Digital logic-formula-notes-final-1
Digital logic-formula-notes-final-1Digital logic-formula-notes-final-1
Digital logic-formula-notes-final-1Kshitij Singh
 
Arduino_Beginner.pptx
Arduino_Beginner.pptxArduino_Beginner.pptx
Arduino_Beginner.pptxshivagoud45
 
A guide to common automation terms
A guide to common automation termsA guide to common automation terms
A guide to common automation termsPratap Chandra
 

Ähnlich wie Dot matrix display design using fpga (20)

Dot matrix module interface wit Raspberry Pi
Dot matrix module interface wit Raspberry PiDot matrix module interface wit Raspberry Pi
Dot matrix module interface wit Raspberry Pi
 
LED MATRIX SCROLLING
LED MATRIX SCROLLING LED MATRIX SCROLLING
LED MATRIX SCROLLING
 
EMBEDDED SYSTEM BASICS
EMBEDDED SYSTEM BASICSEMBEDDED SYSTEM BASICS
EMBEDDED SYSTEM BASICS
 
10617568.ppt
10617568.ppt10617568.ppt
10617568.ppt
 
PRESENTATION ON DATA STRUCTURE AND THEIR TYPE
PRESENTATION ON DATA STRUCTURE AND THEIR TYPEPRESENTATION ON DATA STRUCTURE AND THEIR TYPE
PRESENTATION ON DATA STRUCTURE AND THEIR TYPE
 
456589.-Compiler-Design-Code-Generation (1).ppt
456589.-Compiler-Design-Code-Generation (1).ppt456589.-Compiler-Design-Code-Generation (1).ppt
456589.-Compiler-Design-Code-Generation (1).ppt
 
Varsha patil AISSMS IOIT Pune mca te pu book
Varsha patil AISSMS IOIT Pune mca te pu bookVarsha patil AISSMS IOIT Pune mca te pu book
Varsha patil AISSMS IOIT Pune mca te pu book
 
5th unit Microprocessor 8085
5th unit Microprocessor 80855th unit Microprocessor 8085
5th unit Microprocessor 8085
 
arduinoworkshop-160204051621.pdf
arduinoworkshop-160204051621.pdfarduinoworkshop-160204051621.pdf
arduinoworkshop-160204051621.pdf
 
Ardui no
Ardui no Ardui no
Ardui no
 
Industrial training report of embedded system and robotics
Industrial training report of embedded system and roboticsIndustrial training report of embedded system and robotics
Industrial training report of embedded system and robotics
 
Circuitrix@Pragyan 2015 NITT
Circuitrix@Pragyan 2015 NITTCircuitrix@Pragyan 2015 NITT
Circuitrix@Pragyan 2015 NITT
 
L3-.pptx
L3-.pptxL3-.pptx
L3-.pptx
 
FPGA design with CλaSH
FPGA design with CλaSHFPGA design with CλaSH
FPGA design with CλaSH
 
CLC and SLC with examples.pptx
CLC and SLC with examples.pptxCLC and SLC with examples.pptx
CLC and SLC with examples.pptx
 
14-Bill-Tiffany-SigmaSense-VF2023.pdf
14-Bill-Tiffany-SigmaSense-VF2023.pdf14-Bill-Tiffany-SigmaSense-VF2023.pdf
14-Bill-Tiffany-SigmaSense-VF2023.pdf
 
Digital logic-formula-notes-final-1
Digital logic-formula-notes-final-1Digital logic-formula-notes-final-1
Digital logic-formula-notes-final-1
 
Arduino_Beginner.pptx
Arduino_Beginner.pptxArduino_Beginner.pptx
Arduino_Beginner.pptx
 
A guide to common automation terms
A guide to common automation termsA guide to common automation terms
A guide to common automation terms
 
Iot 101
Iot 101Iot 101
Iot 101
 

Mehr von Hossam Hassan

Software hardware co-design using xilinx zynq soc
Software hardware co-design using xilinx zynq socSoftware hardware co-design using xilinx zynq soc
Software hardware co-design using xilinx zynq socHossam Hassan
 
An Ultra-Low Power Asynchronous-Logic
An Ultra-Low Power Asynchronous-LogicAn Ultra-Low Power Asynchronous-Logic
An Ultra-Low Power Asynchronous-LogicHossam Hassan
 
Introduction to digital signal processing 2
Introduction to digital signal processing 2Introduction to digital signal processing 2
Introduction to digital signal processing 2Hossam Hassan
 
An introduction to digital signal processors 1
An introduction to digital signal processors 1An introduction to digital signal processors 1
An introduction to digital signal processors 1Hossam Hassan
 
Introduction to fpga synthesis tools
Introduction to fpga synthesis toolsIntroduction to fpga synthesis tools
Introduction to fpga synthesis toolsHossam Hassan
 
Public Seminar_Final 18112014
Public Seminar_Final 18112014Public Seminar_Final 18112014
Public Seminar_Final 18112014Hossam Hassan
 
On Being A Successful Graduate Student In The Sciences
On Being A Successful Graduate Student In The SciencesOn Being A Successful Graduate Student In The Sciences
On Being A Successful Graduate Student In The SciencesHossam Hassan
 
Embedded c c++ programming fundamentals master
Embedded c c++ programming fundamentals masterEmbedded c c++ programming fundamentals master
Embedded c c++ programming fundamentals masterHossam Hassan
 
Synthesizing HDL using LeonardoSpectrum
Synthesizing HDL using LeonardoSpectrumSynthesizing HDL using LeonardoSpectrum
Synthesizing HDL using LeonardoSpectrumHossam Hassan
 
NoC simulators presentation
NoC simulators presentationNoC simulators presentation
NoC simulators presentationHossam Hassan
 
Search algorithms master
Search algorithms masterSearch algorithms master
Search algorithms masterHossam Hassan
 
multi standard multi-band receivers for wireless applications
multi standard  multi-band receivers for wireless applicationsmulti standard  multi-band receivers for wireless applications
multi standard multi-band receivers for wireless applicationsHossam Hassan
 

Mehr von Hossam Hassan (13)

Software hardware co-design using xilinx zynq soc
Software hardware co-design using xilinx zynq socSoftware hardware co-design using xilinx zynq soc
Software hardware co-design using xilinx zynq soc
 
An Ultra-Low Power Asynchronous-Logic
An Ultra-Low Power Asynchronous-LogicAn Ultra-Low Power Asynchronous-Logic
An Ultra-Low Power Asynchronous-Logic
 
Introduction to digital signal processing 2
Introduction to digital signal processing 2Introduction to digital signal processing 2
Introduction to digital signal processing 2
 
An introduction to digital signal processors 1
An introduction to digital signal processors 1An introduction to digital signal processors 1
An introduction to digital signal processors 1
 
Introduction to fpga synthesis tools
Introduction to fpga synthesis toolsIntroduction to fpga synthesis tools
Introduction to fpga synthesis tools
 
Public Seminar_Final 18112014
Public Seminar_Final 18112014Public Seminar_Final 18112014
Public Seminar_Final 18112014
 
On Being A Successful Graduate Student In The Sciences
On Being A Successful Graduate Student In The SciencesOn Being A Successful Graduate Student In The Sciences
On Being A Successful Graduate Student In The Sciences
 
Embedded c c++ programming fundamentals master
Embedded c c++ programming fundamentals masterEmbedded c c++ programming fundamentals master
Embedded c c++ programming fundamentals master
 
Synthesizing HDL using LeonardoSpectrum
Synthesizing HDL using LeonardoSpectrumSynthesizing HDL using LeonardoSpectrum
Synthesizing HDL using LeonardoSpectrum
 
NoC simulators presentation
NoC simulators presentationNoC simulators presentation
NoC simulators presentation
 
Search algorithms master
Search algorithms masterSearch algorithms master
Search algorithms master
 
multi standard multi-band receivers for wireless applications
multi standard  multi-band receivers for wireless applicationsmulti standard  multi-band receivers for wireless applications
multi standard multi-band receivers for wireless applications
 
hot research topics
hot research topicshot research topics
hot research topics
 

Kürzlich hochgeladen

BSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptx
BSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptxBSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptx
BSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptxfenichawla
 
Double rodded leveling 1 pdf activity 01
Double rodded leveling 1 pdf activity 01Double rodded leveling 1 pdf activity 01
Double rodded leveling 1 pdf activity 01KreezheaRecto
 
UNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICS
UNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICSUNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICS
UNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICSrknatarajan
 
Thermal Engineering-R & A / C - unit - V
Thermal Engineering-R & A / C - unit - VThermal Engineering-R & A / C - unit - V
Thermal Engineering-R & A / C - unit - VDineshKumar4165
 
VIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 Booking
VIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 BookingVIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 Booking
VIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 Bookingdharasingh5698
 
result management system report for college project
result management system report for college projectresult management system report for college project
result management system report for college projectTonystark477637
 
Intze Overhead Water Tank Design by Working Stress - IS Method.pdf
Intze Overhead Water Tank  Design by Working Stress - IS Method.pdfIntze Overhead Water Tank  Design by Working Stress - IS Method.pdf
Intze Overhead Water Tank Design by Working Stress - IS Method.pdfSuman Jyoti
 
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...roncy bisnoi
 
UNIT-II FMM-Flow Through Circular Conduits
UNIT-II FMM-Flow Through Circular ConduitsUNIT-II FMM-Flow Through Circular Conduits
UNIT-II FMM-Flow Through Circular Conduitsrknatarajan
 
UNIT - IV - Air Compressors and its Performance
UNIT - IV - Air Compressors and its PerformanceUNIT - IV - Air Compressors and its Performance
UNIT - IV - Air Compressors and its Performancesivaprakash250
 
ONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdf
ONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdfONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdf
ONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdfKamal Acharya
 
Booking open Available Pune Call Girls Pargaon 6297143586 Call Hot Indian Gi...
Booking open Available Pune Call Girls Pargaon  6297143586 Call Hot Indian Gi...Booking open Available Pune Call Girls Pargaon  6297143586 Call Hot Indian Gi...
Booking open Available Pune Call Girls Pargaon 6297143586 Call Hot Indian Gi...Call Girls in Nagpur High Profile
 
Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)simmis5
 
Coefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxCoefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxAsutosh Ranjan
 
FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756
FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756
FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756dollysharma2066
 
chapter 5.pptx: drainage and irrigation engineering
chapter 5.pptx: drainage and irrigation engineeringchapter 5.pptx: drainage and irrigation engineering
chapter 5.pptx: drainage and irrigation engineeringmulugeta48
 

Kürzlich hochgeladen (20)

BSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptx
BSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptxBSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptx
BSides Seattle 2024 - Stopping Ethan Hunt From Taking Your Data.pptx
 
Double rodded leveling 1 pdf activity 01
Double rodded leveling 1 pdf activity 01Double rodded leveling 1 pdf activity 01
Double rodded leveling 1 pdf activity 01
 
UNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICS
UNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICSUNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICS
UNIT-IFLUID PROPERTIES & FLOW CHARACTERISTICS
 
Thermal Engineering-R & A / C - unit - V
Thermal Engineering-R & A / C - unit - VThermal Engineering-R & A / C - unit - V
Thermal Engineering-R & A / C - unit - V
 
VIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 Booking
VIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 BookingVIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 Booking
VIP Call Girls Ankleshwar 7001035870 Whatsapp Number, 24/07 Booking
 
result management system report for college project
result management system report for college projectresult management system report for college project
result management system report for college project
 
Call Now ≽ 9953056974 ≼🔝 Call Girls In New Ashok Nagar ≼🔝 Delhi door step de...
Call Now ≽ 9953056974 ≼🔝 Call Girls In New Ashok Nagar  ≼🔝 Delhi door step de...Call Now ≽ 9953056974 ≼🔝 Call Girls In New Ashok Nagar  ≼🔝 Delhi door step de...
Call Now ≽ 9953056974 ≼🔝 Call Girls In New Ashok Nagar ≼🔝 Delhi door step de...
 
Intze Overhead Water Tank Design by Working Stress - IS Method.pdf
Intze Overhead Water Tank  Design by Working Stress - IS Method.pdfIntze Overhead Water Tank  Design by Working Stress - IS Method.pdf
Intze Overhead Water Tank Design by Working Stress - IS Method.pdf
 
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
 
UNIT-II FMM-Flow Through Circular Conduits
UNIT-II FMM-Flow Through Circular ConduitsUNIT-II FMM-Flow Through Circular Conduits
UNIT-II FMM-Flow Through Circular Conduits
 
UNIT - IV - Air Compressors and its Performance
UNIT - IV - Air Compressors and its PerformanceUNIT - IV - Air Compressors and its Performance
UNIT - IV - Air Compressors and its Performance
 
ONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdf
ONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdfONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdf
ONLINE FOOD ORDER SYSTEM PROJECT REPORT.pdf
 
Booking open Available Pune Call Girls Pargaon 6297143586 Call Hot Indian Gi...
Booking open Available Pune Call Girls Pargaon  6297143586 Call Hot Indian Gi...Booking open Available Pune Call Girls Pargaon  6297143586 Call Hot Indian Gi...
Booking open Available Pune Call Girls Pargaon 6297143586 Call Hot Indian Gi...
 
(INDIRA) Call Girl Meerut Call Now 8617697112 Meerut Escorts 24x7
(INDIRA) Call Girl Meerut Call Now 8617697112 Meerut Escorts 24x7(INDIRA) Call Girl Meerut Call Now 8617697112 Meerut Escorts 24x7
(INDIRA) Call Girl Meerut Call Now 8617697112 Meerut Escorts 24x7
 
Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)
 
Call Girls in Ramesh Nagar Delhi 💯 Call Us 🔝9953056974 🔝 Escort Service
Call Girls in Ramesh Nagar Delhi 💯 Call Us 🔝9953056974 🔝 Escort ServiceCall Girls in Ramesh Nagar Delhi 💯 Call Us 🔝9953056974 🔝 Escort Service
Call Girls in Ramesh Nagar Delhi 💯 Call Us 🔝9953056974 🔝 Escort Service
 
Coefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxCoefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptx
 
FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756
FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756
FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756
 
(INDIRA) Call Girl Bhosari Call Now 8617697112 Bhosari Escorts 24x7
(INDIRA) Call Girl Bhosari Call Now 8617697112 Bhosari Escorts 24x7(INDIRA) Call Girl Bhosari Call Now 8617697112 Bhosari Escorts 24x7
(INDIRA) Call Girl Bhosari Call Now 8617697112 Bhosari Escorts 24x7
 
chapter 5.pptx: drainage and irrigation engineering
chapter 5.pptx: drainage and irrigation engineeringchapter 5.pptx: drainage and irrigation engineering
chapter 5.pptx: drainage and irrigation engineering
 

Dot matrix display design using fpga

  • 1. Chapter:9 Dot-Matrix Display Design Using FPGA By: Hossam Hassan PhD Student, MSIS Lab, Chungbuk National University MSIS
  • 2. Objectives • In this lab we will deal with the dot-matrix display which used to display information on many devices requiring a simple display device with limited resolution. • We will write Verilog code to simulate how to drive dot-matrix display then synthesis the code to run on FPGA board.
  • 3. Introduction • Internally, the LEDs are organized in a matrix. • Here's a 5x7 display internal wiring. • Dot Matrix has two types: • Common Cathode Type: • a common anode for LEDs in a row - all of the anodes in each row is common • Common Anode Type: • a common cathode for LEDs in a row – all the cathodes in each row is common.
  • 4. Theory of LED dot matrix display • In a dot matrix display, multiple LEDs are wired together in rows and columns. This is done to minimize the number of pins required to drive them. • For example, a 5×7 matrix of LEDs (shown below) would need 35 I/O pins. By wiring all the anodes together in rows (R1 through R7), and cathodes in columns (C1 through C5), the required number of I/O pins is reduced to 16. Each LED is addressed by its row and column number. In the figure below, if R4 is pulled high and C3 is pulled low, the LED in fourth row and third column will be tuned on. Characters can be displayed by fast scanning of either rows or columns. Common Anode
  • 5. Theory of LED dot matrix display • Suppose, we want to display the alphabet A. • We will first select the column C1 (which means C1 is pulled low in this case), and deselect other columns by blocking their ground paths (one way of doing that is by pulling C2 through C5 pins to logic high). • Now, the first column is active, and you need to turn on the LEDs in the rows R2 through R7 of this column, which can be done by applying forward bias voltages to these rows. • Next, select the column C2 (and deselect all other columns), and apply forward bias to R1 and R5, and so on. • Therefore, by scanning across the column quickly (> 100 times per second), and turning on the respective LEDs in each row of that column, the persistence of vision comes in to play, and we perceive the display image as still. Common Anode
  • 6. Theory of LED dot matrix display • The table below gives the logic levels to be applied to R1 through R7 for each of the columns in order to display the alphabet ‘A’.
  • 7. Verilog implementation • To run our code we have 4 Inputs and 5 Outputs. • First, there are RESET and Clock can be entered by default in the FPGA, • the KEY and Mode_Switch as an input to select Mode are needed to control the Dot-Matrix (same as previous labs ). • Finally, the Dot-Matrix is used for the output. • (LEDs and 7-Segments used same as the previous labs). • Top Module of the Dot-Matrix example indicated the Input/Output Ports: 2 Dot-Matrix Display
  • 9. Verilog implementation: dot.v Dot Matrix Registers Declaration Clock Division Dot Matrix of Control Related COL Counter Related Data Counter to be displayed on Dot Matrix
  • 10. Verilog implementation: dot.v Dot Matrix COL, RAW Data Processing Dot Matrix COL, RAW Data Print
  • 12. Verilog Behavioral Simulation • To test the operation of the dot-matrix and the functionality of our code we have to run behavioral simulation as following steps: • Define the IOs for the Design Under Test (DUT) to provide inputs and see the expected output on the ISim waveform. • We define the input in the testbench as register type, so we can provide our inputs for test.
  • 13. Test bench source code -Registers and Wires Declarations to indicate the IOs: -Instantiate the Unit Under Test (UUT): -Clock Generation:
  • 14. Test bench source code -Initialize our test cases: Screen Shot of the running simulation
  • 15. Homework • Do the following exercise and explain your Verilog code with simulation, and test on the FPGA. • Run the Dot-Matrix Project and display the same numbers using 7- Segments and Dot-Matrix. • Run the Dot-Matrix Project and display different shapes. • Run the Dot-Matrix Project and display your name moving character by character. (Challenge)
  • 16. An LED matrix display scanning by rows to make the letter W