SLIDE SHOWS THE DIFFERENCE BETWEEN ASIC AND FPGA

2. FPGA
HISTORY
 Field programmable gate arrays(FPGAs)arrived in
1984 as an alternative to programmable logic
devices(PLDs) .
 As their name implies ,FPGAs offer the significant
benefit of being readily programmable.
 FPGAs fill a gap between discrete logic and the
smaller PLDs on the low end of the complexity scale
and costly custom ASICs on the high end.

3.  A field-programmable gate array (FPGA) is
an integrated circuit designed to be configured by a
customer or a designer after manufacturing – hence
"field-programmable". The FPGA configuration is
generally specified using a hardware description
language (HDL)
FPGA

4.  The architecture of FPGA is very simple than other
programmable devices
Elements of FPGA
The basic elements of an Field Programmable Gate Array
are:
 Configurable logic blocks(CLBs)
 Configurable input output blocks(IOBs)
 Two layer metal network of vertical and horizontal lines for
interconnecting the CLBS and FPGAs (programmable
interconnect)
FPGA

5.  A simple modern architecture of FPGA is shown
below:

6. FPGA

7.  Just about all FPGAs include a regular,
programmable, and flexible architecture of logic
blocks surrounded by input/output blocks on the
perimeter. These functional blocks are linked
together by a hierarchy of highly versatile
programmable interconnects.

8. Configurable logic blocks (CLBs)
 The configurable logic block which is RAM based
or PLD based is the basic logic cell. It consists of
registers (memory), muxes and combinatorial
functional unit.
 An array of CLBS are embedded within a set of
vertical and horizantal channels that contain
routing which can be personalized to
interconnect CLBs.

9.  The following figure represents the
architecture of a single CLB.

10. Configurable Input / Output logic locks
(IOBs):
 CLBs and routing channels are surrounded by a
set of programmable I/Os which is an
arrangement of transistors for configurable I/O
drivers.

11. Programmable interconnects
 These are un programmed interconnection
resources on the chip which have channeled
routing with fuse links.
 Programmable highly interconnect matrix is
available. In this case the design is that of the
interconnections and communications only.

12.  The following figure represents the Row-
Column architecture of programmable
interconnect.

13. FPGA

14. Different FPGA Vendors
Though there are various FPGA vendors in the world
market only two or three manufacturers are well known
in the industry. For example :
1. Xilinx : Founded by Ross Freeman, original
inventor of FPGAs in 1984.
Sparten II,IIE,Sparten III,Virtex …
2. Altera: Altera cyclone II FPGA and
associated design, software Quartus II
3. Actel :

16. FPGAs with different packages

17. Advantages
 Faster time-to-market: No layout, masks or other
manufacturing steps are needed for FPGA design.
Readymade FPGA is available and burn your HDL code
to FPGA ! Done !!
 No NRE (Non Recurring Expenses): This cost
is typically associated with an ASIC design. For FPGA this
is not there. FPGA tools are cheap. (sometimes its free !
You need to buy FPGA.... thats all !). ASIC you pay huge
NRE and tools are expensive.

18. Simpler design cycle: This is due to software that
handles much of the routing, placement, and timing. Manual
intervention is less.The FPGA design flow eliminates the
complex and time-consuming floor planning, place and
route, timing analysis.
More predictable project cycle: The FPGA design
flow eliminates potential re-spins, wafer capacities, etc of
the project since the design logic is already synthesized and
verified in FPGA device.
Advantages

19. Advantages
Field Reprogramability: A new bitstream ( i.e. your
program) can be uploaded , instantly. FPGA can be
reprogrammed in a snap while an ASIC can take more than
4-6 weeks to make the same changes.
Reusability: Reusability of FPGA is the main advantage.
Prototype of the design can be implemented on FPGA
which could be verified for almost accurate results so that
it can be implemented on an ASIC. If design has faults
change the HDL code, generate bit stream, program to
FPGA and test again.
FPGAs are good for prototyping and limited production.If
you are going to make 100-200 boards it isn't worth to
make an ASIC.

20. Dis Advantages
Power consumption in FPGA is more. You don't have any
control over the power optimization. This is where ASIC
wins the race !
You have to use the resources available in the FPGA. Thus
FPGA limits the design size.
Good for low quantity production. As quantity increases
cost per product increases compared to the ASIC
implementation.

21. FPGA DESIGN TOOLS
 There are two important design tools
available in the market
 verilog
 VHDL (Very high speed integrated circuit
hardware descriptive language)

22. Verilog
 Verilog HDL originated in 1983 at Gateway design
automation.
 Today, Verilog HDL is an accepted IEEE standard.In
1995,the original standard IEEE 1364-1995 was
approved. IEEE 1364-2001 is the latest verilog HDL
standard that made significant improvements to the
original standard.

23. Verilog

24. VHDL
VHDL is a language for describing digital
electronic systems. It arose out of the United
states government’s very high speed
integrated circuits (VHSIC) program initiated
in 1980

25. VHDL

26. ASICs
• ASIC - Application Specific Integrated Circuit
– In Integrated Circuit (IC) designed to perform a
specific function for a specific application
– An application-specific integrated circuit (ASIC) , is
an integrated circuit (IC) customized for a particular
use, rather than intended for general-purpose use.
For example, a chip designed to run in a digital voice
recorder is an ASIC

27. NDG-L01-2
CSE 324 FPGA based System Design-
Introduction 27
Types of ASICs
Full-Custom ASICs: Possibly all logic cells and all mask layers customized
Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized

28. Advantages
 Lower unit costs: For very high volume
designs costs comes out to be very less.
Larger volumes of ASIC design proves to be
cheaper than implementing design using
FPGA
 ASICs are faster than FPGA: ASIC gives
design flexibility. This gives enormous
opportunity for speed optimizations.

29. Advantages
 Low power: ASIC can be optimized for
required low power. There are several low
power techniques such as power gating, clock
gating, multi vt cell libraries, pipelining etc are
available to achieve the power target.
 In ASIC you can implement analog circuit,
mixed signal designs. This is generally not
possible in FPGA.
 In ASIC DFT (Design For Test) is inserted. In
FPGA DFT is not carried out

30. Dis Advantages
Time-to-market: Some large ASICs can take a year or
more to design. A good way to shorten development
time is to make prototypes using FPGAs and then
switch to an ASIC.
Design Issues: In ASIC you should take care of DFM
issues, Signal Integrity isuues and many more. In
FPGA you don't have all these because ASIC designer
takes care of all these.
Expensive Tools: ASIC design tools are very much
expensive. You spend a huge amount of NRE

31. FPGA DESIGN FLOW
• Full-Custom ASICs
• Standard-Cell–Based ASICs
• Gate-Array–Based ASICs
• Channeled Gate Array
• Channelless Gate Array
• Structured Gate Array
• Programmable Logic Devices
• Field-Programmable Gate Arrays

32. Design Specification
Specifications comes first, they describe abstractly the
functionality, interface, and the architecture of the
digital IC circuit to be designed.
Behavioral description
It is created to analyze the design in terms of
functionality, performance, compliance to given
standards, and other specifications.
RTL description
It is done using HDLs. This RTL description is simulated
to test functionality. From here onwards we need the
help of EDA tools.
FPGA DESIGN FLOW

33. Logic Synthesis
RTL description is then converted to a gate-level netlist
using logic synthesis tools. A gate-level netlist is a
description of the circuit in terms of gates and connections
between them, which are made in such a way that they
meet the timing, power and area specifications.
FPGA DESIGN FLOW

34. FPGA DESIGN FLOW

35. FPGA DESIGN FLOW

36. FPGA DESIGN FLOW
Logic Synthesis

37. FPGA DESIGN FLOW

38. FPGA DESIGN FLOW

39. FPGA DESIGN FLOW

40. ASIC DESIGN FLOW