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Xilinx Edge Compute using Power 9 /OpenPOWER systems
- 1. © Copyright 2018 Xilinx - Xilinx Alveo for Cloud & Edge Computing March 2020 Jens Stapelfeldt – BDM EMEA Jens.Stapelfeldt@Xilinx.com LinkedIn: www.linkedin.com/in/JensStapelfeldt Xilinx - Building the Adaptable Intelligent World
- 2. © Copyright 2018 Xilinx Page 2 Jens Stapelfeldt BDM DC – EMEA Jens technical background: - 3 Y ASIC designer - 12 Y Busines Manager CE and Trainer for Doulos in CE and ARM ATC WW - Design methodology (Verification, SystemC,..) - (V)HDL, FPGA, ARM Achritecture (ARM7 - Cortex-M to Cortex-A) - 5 Y Sr. Embedded FAE at TI - Sitara, DaVinci, OMAP, Keystone II - Industrial App. (IoT, Industrial Ethernet (EtherCAT, ProfiNet,..), Camera Vison ..) - Since Oct. 2016 Tech Sales Lead for Xilinx in EMEA - Supporting DACH, EE, Russia, Israel, India - 2019 BDM Data Center - Part time MBA in Bremen with weeks in Hong Kong, Cambridge, Dublin Business school! MBA: In May 2018 I finished my MBA with Master Thesis in International Marketing looking into about 600 AI/ML Start-ups in EMEA! LinkedIn Article: https://www.linkedin.com/pulse/analysing-europes-aiml-start-up-landscape-using-jens-stapelfeldt/ Jens.Stapelfeldt@Xilinx.com LinkedIn: www.linkedin.com/in/JensStapelfeldt
- 3. © Copyright 2018 Xilinx Headquarters R&D and Engineering Sales and Support R&D and Sales Fab & Manufacturing Partners We Are Xilinx Founded in 1984 >> 3 Customers 60K+ Employees Worldwide ~5,000 Industry Firsts 60+ Patents 4,400+ Revenue (FY19) $3.06B Hyderabad, India Dublin, Ireland Singapore San Jose, CA Longmont, CO
- 4. © Copyright 2018 Xilinx Our Legacy: A History of Innovation and Industry Firsts >> 3 World’s First Fabless Semiconductor Company World’s First FPGA First Integrated Processor in an FPGA First HW/SW Programmable SoC World’s First 2.5D IC FPGA First ASIC-Strength Design Suite First Multi-Processing SoC (MPSoC) SDx Development Environments First RFSoC First Adaptive Compute Acceleration Platform (ACAP)
- 5. © Copyright 2018 Xilinx Industrial & Vision Consumer Wireless Communications AutomotiveProAV & Broadcast Wired Communications Test & Measurement, and Emulation Data Center Healthcare & Sciences Aerospace & Defense Our Customers are Innovators in… >> 5
- 6. © Copyright 2018 Xilinx DAWN OF AI ˃ Adding new intelligence into applications ˃ In all industries, from endpoints to edge to cloud ˃ Need for accelerated AI processing everywhere EXPLOSION OF DATA ˃ Video & image content ˃ 90% unstructured ˃ Need for higher throughput & real-time computing COMPUTING AFTER MOORE’S LAW ˃ Speed of innovation outpacing silicon cycles ˃ Breadth of apps require different architectures ˃ Need for heterogeneous computing with accelerators The Next Frontier of Adaptive Compute Three Big Challenges >> 6
- 7. © Copyright 2018 Xilinx Industry Trend: Heterogeneous Compute Cache Cache Cache 1980-2000 2x/ 1.5y process à Dennard scaling 2000-2010 2x/ 3.5y multithreading à Amdahl’s law 2010-2020 2x/ 10y density à Moore’s law SINGLE CORE MULTICORE HETEROGENEOUS ADAPTIVE HETEROGENEOUS Cache Scaling from: Silicon process Architecture-aware software Software-aware architecture AcceleratorCPU Multicore CPU Multicore CPU FPGA, ACAP
- 8. © Copyright 2018 Xilinx Xilinx (HW & Software) Platform Transformation page 9 2012 2019 #DEVELOPERS OS and Firmware SDK AI inference Acceleration Vitis Unified Software Platform SDSoC, Embedded SDAccel, Data Center (FaaS, Alveo) Vivado Vivado FPGA SoC MPSoC RFSoC ACAP Device Category Alveo acceleration boards
- 9. © Copyright 2018 Xilinx Xilinx in Data Center
- 10. © Copyright 2018 Xilinx Adaptable Acceleration for Data Center >> 12 HIGHEST PERFORMANCE Maximum throughput and ultra-low latency with optimized, domain-specific architectures VIDEOANALYTICS MONITORING & SECURITY LIFE SCIENCES DATABASE Apps MACHINE LEARNING SEARCH NETWORKSTORAGE COMPUTE ADAPTABLE Adapt faster to evolving workloads by reconfiguring your hardware VERSATILE Accelerate a wide range of use cases across Compute, Storage, and Networking FINANCIAL KEY VALUE COMPRESSION VIRTUALIZATION LOW LATENCY TCP
- 11. © Copyright 2018 Xilinx Xilinx - from Device to Alveo in the cloud (FaaS) >> 13 Devices Production Boards FPGA as a Service (FaaS) Seamless portability of applications, same compute platform can run on all Xilinx supports multiple engagement models with our platform based approach
- 12. © Copyright 2018 Xilinx Comprehensive Software and Hardware Stack for All Developers >> 14 Frameworks Data Scientists & AI Developers Libraries, Compilers, Middleware Application Developers Firmware And Runtime Software Developers Integrated Development Environment Hardware and Software Developers Hardware Devices and Accelerator Cards
- 13. © Copyright 2018 Xilinx Xilinx Alveo Product Lineup 15 1,304k LUTs Dual slot, full height 8GB HBM2, 460GB/sec 2x QSFP 28 (100GbE) PCIe Gen3, Gen4, CCIX < 225W 1,182k LUTs Dual slot, full height 64GB DDR, 77GB/sec 2x QSFP 28 (100GbE) PCIe Gen3 < 225W 1,728k LUTs Dual slot, full height 64GB DDR, 77GB/sec 2x QSFP 28 (100GbE) PCIe Gen3 < 225W U280U250U200 UltraScale+ ArchitectureUltraScale+ Architecture UltraScale+ Architecture U50 872k LUTs Single slot, half height 8GB HBM2, 460GB/sec 1x QSFP 28 (100GbE) PCIe Gen3, Gen4, CCIX < 75W UltraScale+ Architecture
- 14. © Copyright 2018 Xilinx Xilinx Alveo U50 Accelerator 16 UltraScale+ Architecture Low-profile form factor 8GB HBM2 Memory, 460GB/sec QSFP 28 (100GbE) PCIe Gen4, CCIX, PCIe Gen3 < 75W 4x10 Gbps 4x25 Gbps 1x100bps
- 15. © Copyright 2018 Xilinx Card Alveo U50 Primary Application Fintech + Storage + Database + ML FPGA Design XCU50 CCIX Yes Device VCCINT 0.85V Width Single slot Form Factor (Passive) HHHL Memory Target 8 GB HBM Memory Config Dual Stack, 32 pseudo-ports PCIe 2x Gen4x8, 1x Gen4x8, Gen3x16, CCIX Network I/F 2x SFP- DD* or 1X QSFP28 Thermal Passive Power (Max TDP) 75W KLuts 872K Alveo U50 – Low Profile Acceleration Card Database Fintech Storage Machine Learning 17 * During ES, U50 card will have 2 SFP-DD ports
- 16. © Copyright 2018 Xilinx Over 10X improvement in performance and power efficiency for critical data center applications Most advanced, adaptable platform for accelerating compute, networking, and storage Built for any server, any cloud Alveo U50: Industry’s First Adaptable Accelerator Built for Cloud & Edge Data Centers 18
- 17. © Copyright 2018 Xilinx Xilinx Alveo U25 SmartNIC Gen 3 x16 PCIe (dual Gen 3 x8) 2 x 25GbE MACMAC 2x25G SFP28 FPGA Flash Memory SFP28 Features Comments FPGA Zynq XCU25 Network Interface 2x SFP28 DAC or Optical Form Factor HHHL, single slot Cooling Passive Processor Quad A53 1.5Ghz Power <75W Host Interface PCIe Gen3 x16 Bifurcated to 2x Gen3 x8 Memory 1x 2GB x 40 (FPGA) 1x 4GB x 72 (Processor) Manageability Satellite Controller KLUTs 523K Micro Controller ACCELERATION KERNELS Solarflare X2 Ethernet Controller PCIe Gen3 x8 25G 25G Gen3 x8 PLDDRPSDDR 2GB 4GB 19
- 18. © Copyright 2018 Xilinx Alveo U25 use case exp. - Distributed NIC Firewall Use Case • Key extraction logic pulls out multiple packet fields for the security lookup • Algorithmic STCAM used to lookup against Access Control List • Blacklist Flows can be dropped immediately • Whitelist flows can be passed through (control plane on ARM can be used to provide stateful firewall operation) Ethernet PCIe DDR U25 Plugin Image Detect Accelerator Plugins ARM ARM Ethernet Plugin Interface FabricEthernet Ethernet PCIe (for loading/control) ARM ARM X2 NICACL Lookup ACL Lookup Key Extract Key Extract 21
- 19. © Copyright 2018 Xilinx Alveo SmartNIC to implement Zero-Trust Security in FactoryCloud
- 20. © Copyright 2018 Xilinx23 Layers 1. Communication (TSN, RT-Ethernet, 5G.. 2. Silicon (CPU, GPU, FPGA (Zynq), ACAP.. 3. OS (Linux-OSADL, QNX, VXWorks,.. 4. Middleware (RT OCP UA, OneM2M, .. 5. Information (Companion Spec., DT/AI 6. Application (vPLC, AI, .. Cross Layer I. Security (IPSec or SSL/TLS bulk crypto kernel) II. Real-Time (deterministic Low latency, TSN, RT-Ethernet, III. Acceleration (ML, Videoframe decoding, (SMV)) IV. Virtualization (SmartNIC, SDN, vPLC) V. Management (Business Analytics (BA), DT) Edge computing Architecture Model - in Layers See: Jens Smart-Factory talk from XDF in Dec. https://ptdrv.linkedin.com/a6zvrc4
- 21. © Copyright 2018 Xilinx Xilinx for AI/ML Inference and VITIS AI SW-tools
- 22. © Copyright 2018 Xilinx AI Inference Explosion from Cloud to Edge Training Data Center Inference Edge InferenceTAM $B Barclays Research, Company Reports May 2018 2016 2017 2018 2019 2020 2021 2022 2023 30 20 10 Genomics Video Analytics Healthcare Finance Smart City Smart Retail Autonomous Driving Security AI
- 23. © Copyright 2018 Xilinx Growing AI Pervasiveness from Cloud to Edge >> 26 Classification Object Detection Speech Recognition Recommendation Engine Anomaly Detection CNN RNN, LSTM MLP Diverse AI models from Cloud, to Network, to Edge Data Analytics RF, LR
- 24. © Copyright 2018 Xilinx Xilinx - Flexible and Adaptable Memory Hierarchy is the Key! ˃ Rigid memory hierarchy & SW defined dataflow ˃ High “data locality” required for workload efficiency ˃ “Batching” improves efficiency at expense of latency 100X 1X Latency : Power 10X 1X 2X 80X CPU/GPU corereg corereg corereg corereg Block 0 corereg corereg corereg corereg Block 1 corereg corereg corereg corereg Block N Global Mem (Off-chip HBM / GDDR) Shared Mem / L1 Cache Shared Mem / L1 Cache Shared Mem / L1 Cache L2 Cache Memory Compute Memory Hierarchy (Interconnect) Fixed Adaptable Memory Compute Memory Hierarchy Xilinx Global Mem (if needed) UltraRAM UltraRAM BRAM BRAM BRAM BRAM LUTRAM LUTRAM LUTRAM LUTRAM LUTRAM LUTRAM LUTRAM Kernel A Kernel B Kernel C BRAM ˃ Adaptable memory hierarchy & datapath ˃ ~5X more on-chip memory ˃ Max throughput, min latency – no batching required ML InferDB - SQL VideoGenomics 4X DB - RegEx 3X 3X 6X Resultant Workload Speed-Up vs. CPU / GPU 6X
- 25. © Copyright 2018 Xilinx Ø All Developers Can Build and Deploy on All Platforms Build Deploy Ultrascale AlveoZynq Data Center Rack Embedded Developers Enterprise Application Developers Enterprise Infrastructure Developers Data & AI Scientists Xilinx new SW platform Vitis - Unified Software Platform
- 26. © Copyright 2018 Xilinx Hardware Developers Software Developers AI & Data Scientists Development Platforms for ALL Developers
- 27. © Copyright 2018 Xilinx Xilinx runtime libraries (XRT) Vitis target platform Domain-specific development environment Vitis core development kit Vitis accelerated libraries OpenCV Library BLAS Library Vitis AI Vitis Video Partners Genomics, Data Analytics, And moreFinance Library Analyzers DebuggersCompilers Vitis: Unified Software Platform
- 28. © Copyright 2018 Xilinx Frameworks Vitis AI development kit Vitis AI models Deep Learning Processing Unit Vitis AI: Deep Learning Acceleration Xilinx runtime library (XRT) AI Optimizer AI Quantizer AI Compiler AI Profiler AI Library
- 29. © Copyright 2018 Xilinx Shell Hardware Developers Application Software Developers AI Scientists (iterations in minutes) Embedded Developers Putting it All Together
- 30. © Copyright 2018 Xilinx Xilinx Alveo Ecosystem Overview - and used cases >> 34
- 31. © Copyright 2018 Xilinx CLOUD ON-PREMISE HPC Video and Imaging Data Analytics Fintech Public Sector SaaS Developers IP & App Developers Platform Providers End Customers Xilinx: The Clear Leader in FPGA Accelerated Computing MSC Azure
- 32. © Copyright 2018 Xilinx >> 36 Database and Data Analytics Bigstream Accelerated Apache Spark BlackLynx Solving Complex Analytics Challenges SumUp Analytics Text Analytics Titan IC* RXP Accelerated Search & Analytics Machine Learning Xelera Speaker Recognition Random Forest InAccel Accelerated ML Suite Xilinx Vitis AI Boon Logic Sentry ND Cyber-Defense Mipsology* Zebra for Accelerating Neural Network Inference Video and Imaging Aupera Video + MLAppliance : Contact Ben Runyan Boston The Boston Stream+ Video Encoding Appliance Deepoly ThunderImage: Image Transcoding OBS solution Financial Technology Xilinx Vitis Quant Finanace Libraries Algo-Logic* Tick-to-Trade Pre-Trade Risk Check Enyx* Enyx 10G Ultra-Low latency MAC + PCS IP core NTT Disruption Accelerated Market Risk * Vivado Design flow Xilinx Eco System partner solutions – ready to go
- 33. © Copyright 2018 Xilinx Xilinx Alveo solution Briefs available Go to - https://www.xilinx.com/support/documentation-navigation/documentation-keyword-search.html#q=xilinx IBM Xilinx Auto-AI Images & Video Solution Brief: https://www.xilinx.com/publications/ solution- briefs/partner/openpower.pdf
- 34. © Copyright 2018 Xilinx PowerAI Vision: Auto-AI for Image & Video 38 https://www.xilinx.com/video/events/ibm-powerai-vision-inference-accelerated-by-xilinx-vitis-ai.html
- 35. © Copyright 2018 Xilinx Single Click Deployment of Trained Models to FPGA 39 IBM Xilinx Auto-AI Images & Video Solution Brief: https://www.xilinx.com/publications/solution-briefs/partner/openpower.pdf
- 36. © Copyright 2018 Xilinx Different Inference End Points – edge use cases 40 IBM Xilinx Auto-AI Images & Video Solution Brief: https://www.xilinx.com/publications/solution-briefs/partner/openpower.pdf
- 37. © Copyright 2018 Xilinx Live Video Transcoding 41 5x Alveo U50 NGCodec HEVC Very-High Quality 20x 1080p30 One Alveo U50 Server Alveo U50 HEVC Video Compression 23x Lower Power Cost 8x Lower HW Cost 40x Xeon Gold H.265 very-high quality 20x 1080p30 20x Dual CPU Servers 20x Throughput Per Node Simplified and Lower Cost Infrastructure
- 38. © Copyright 2018 Xilinx Build: Extensive, Open Source Libraries 400+ functions across multiple libraries for performance-optimized out-of-the-box acceleration Vision & Image Finance Data Analytics & Database Data Compression Data Security Math Linear Algebra Statistics DSP Data Management Domain-Specific Libraries Common Libraries
- 39. © Copyright 2018 Xilinx Compilers AI optimization LLVM User Since 2001 Contributor Since 2007 Now Core to Xilinx Strategy Committed to Open Source 2007 Contributions2019 Runtime Libraries AI Models 20192019
- 40. © Copyright 2018 Xilinx High Throughput AND Low Latency Matches the Fast Pace of AI Innovation Accelerates the Whole Application Comprehensive AI Software Platform Xilinx Industry-Leading AI Inference Whole App Acceleration is optimized hardware acceleration of both AI inference and other performance-critical functions, tightly coupled in a single device WHOLE APPLICATION ACCELERATION 44
- 41. © Copyright 2018 Xilinx Thanks Q & A
- 42. © Copyright 2018 Xilinx Adaptable. Intelligent.
- 43. © Copyright 2018 Xilinx Adaptable. Intelligent.
- 44. © Copyright 2018 Xilinx >> 48
- 45. © Copyright 2018 Xilinx >> 49
- 46. © Copyright 2018 Xilinx >> 50