The document describes several passes that are performed by PTXOptimizer to optimize PTX code for GPU execution. The passes include subkernel formation, barrier removal, register allocation, and MIMD thread scheduling. The goals of the passes are to reduce kernel loading time, reduce thread waiting at barriers, increase data sharing between threads, and enable more parallel thread execution.

3. RemoveBarrierPass

4. LinearScanRegisterAllocationPass

5. MIMDThreadSchedulingPass

6. Module Kernel DFG0 CFG0 SubkernelFormationPass 2 Step1. Assign top kernel for all CFG0 CFG1 CFG2 a b + a a c entry exit

7. Module Kernel 0 Module Kernel 0 Kernel 1 Kernel 0 Kernel 1 kernel_0 kernel_1 Schedule assign Sub Kernels assign SubkernelFormationPass 3 CFG0 CFG1 CFG2 CFG2

9. 1) start at a kernel entry point that dominates all remaining blocks

10. 2) create a strongly connected subgraph with N instructions and no barriers

11. a) This is a new kernel

12. 3) For all edges leaving the graph

13. a) save all live registers

14. b) save the target block's id

15. c) create a new scheduler block includes an indirect branch to each

16. of the targets

17. d) redirect each edge to the kernel exit point

18. e) create a new kernel rooted in the new scheduler block, goto 1 Ref: SubkernelFormationPass.cpp

21. Dominator tree

22. Control tree

24. Reduce the kernel loading and Paralleling

25. Ps: that is a trade off in “fork” “join” with kernel communication

26. RemoveBarrierPass 1 Ref: ocelot-pact.pdf

33. Instruiction *IT= new Instruction(IR::FunctionCall)

34. Kernel->cfg()->insert(IT);

36. IT->a() = IR::addressType // source register

40. Reduce the thread waiting time in each barrier synchronous check.

43. Preprocessor

44. Successor

47. More data sharing

49. j = j + 1;

50. setp.lt.s32 p, i, n; // compare i to n

51. @!p bra L1; // if false, branch over

52. add.s32 j, j, 1;

53. L1: ... j=j+1 j=j+1

56. Post = kernel->post_dominator_tree();

58. kernel->Instruction->Insert(IT);

60. kernel->PTX()->update();

62. More parallelism to thread access