9. Active-HDL ™ 8.2 9
RTL Design and Simulation
Common-Kernel Mixed Language
Simulator
Languages: VHDL, Verilog®, SystemVerilog
(Design), SystemC & EDIF
HDL Design Tools: Design entry, Design
Creation, Code2Graphics™, Block and State
Diagram, Waveform editor, stimulus
generation, Language templates & auto-
complete, scripting, legacy design support.
Design Flow Manager: use popular third-
p y
party tools throughout the design flow within
g g
the same FPGA environment.
Debugging: Code execution tracing,
Waveform/Compare, Memory Viewer, Xtrace,
Advanced Dataflow and Profiler.
Coverage: C d C
C Code Coverage, T
Toggle &
l
Functional Coverage.
Additional Interfaces: DSP/HDL algorithm
MATLAB® and Simulink® Interfaces & Zuken
CADSTAR PCB Design
Assertion and Coverage(OPTION)
SystemVerilog PSL & OVA support.
Dedicated Assertion viewer, coverage,
breakpoint editor.
10. Riviera-PRO™ 2009.06 10
Fast RTL Simulation
Advanced Verification
Common-Kernel Mixed Language Simulator
Multi-Platform (32/64bit Linux®, Windows®)
ut at o (3 /6 b u , do s )
Languages: VHDL, Verilog® , SystemVerilog
(Design, Verification & Assertions), Assertions (SVA,
OVA, PSL), SystemC & EDIF 200
Debugging: Code execution tracing,
Waveform/Compare,
Waveform/Compare Memory Viewer, Xtrace,
Viewer Xtrace
Advanced Dataflow and Profiler. Universal
HDL/SystemC code level Debugging, Post-
Simulation Debugging.
Code Coverage, Functional Coverage,
Toggle/Expression/Branch coverage.
Assertion and Coverage based verification.
Assertion waveform viewer, functional coverage,
breakpoint editor.
Co-Simulation: DSP/HDL algorithm MATLAB® and
Simulink® Interfaces
ALINT Design Rule Checking: VHDL, Verilog,
Mixed language designs, Violation Viewer,
Configuration Manager
Third-Party support: Synopsys SmartModels™
SWIFT,
SWIFT SpringSoft® FSDB Denali® Memory
FSDB,
Models, Xilinx Secure IP OVM 2.0 Support –Future.
Simulation Regression Manager (SFM)
11. ALINT™ 2009.06 11
Design Rule Checking
ALINT is a robust environment for
Design R l Ch ki in:
D i Rule Checking i
VHDL or Verilog Designs
Mixed-Language Designs
300+ rules from STARC® 2006
Design Guides and Aldec native
Interactive Debugging
Violation Viewer
HDL Editor
Ruleset Editor
Policy Editor
Custom Rules creation
Tracking,
Tracking Results Analysis Reporting
Analysis,
Design and library management
12. HES™ 2009.07
Hardware Emulation System
ASIC, FPGA,
ASIC FPGA SOC
Emulation 1-100MHz
Acceleration 10X or more
Prototyping 1-100MHz
Simulator Independent
L
Languages: VHDL, Verilog®
VHDL V il ® ,
SystemC/C/C++, Assertions, EDIF
Transaction Level Interface
(SCE-MI 2.0, SystemC C/C++)
(SCE MI 2 0 S t C C/C )
Ultra-Fast DebuggerTM
off-the-shelfDINI and HAPS
hardware support
13. DO-254/CTS™
End-to-End Verification of Avionic
Designs for DO-254/ED80 Compliance
Advantages
• At-Speed Design Verification in Target Devices
• Supports Actel , Altera® Lattice® QuickLogic® and
Actel™ Altera®, Lattice®,
Xilinx®
• Automatic Test Vectors Generation for Target Devices
• Auto-Capture and Analysis of results at all Design Stages
• Easy Design Requirements Traceability
• Independent EDA Tool Assessment
p
• Significantly shortens Device Verification Time
Included Software
• Aldec HDL Simulator (optional)
• Aldec Waveform Viewer
•C d C
Code Coverage
• Design Rule Checking
Included Hardware
• PCI/PCIe Motherboard
• Custom Daughterboard with target device
• CVT Application (TVD, VT, drivers, API diagnostic
(TVD VT drivers API,
designs and
Compliance documentation)
DO-254/CTS supports the “Design Assurance Guidance for Analysis
Airborne Electronic Hardware” ( DO-254/ED80) chapter 6.2 Results Compare
“Verification Process” and chapter 11.4 “Tool Assessment and
p EDA Tool Qualification
Qualification Process”. Levels A-D.
14. ALDEC INDIA OPERATIONS
Aldec India office is based in Bangalore.
P-186, Sector 10
Jiwan Bima Nagar
Bangalore 560075
India
Focusing mainly on marketing and customer support.
Visit us at: www.aldec.com
15. CHANNEL PARTNERS IN INDIA
www.amdlcorp.com
a d co p co
Headquartered in Bangalore
Offices in Delhi, Mumbai, Hyderabad and other major cities
Its customer base includes major Corporate and Defense
establishments, Software Technology parks, MNC's and Super-
Specialty Hospitals.
p y p
The company's commitment to technology and support has
been its areas of strength and the reason for its customers to
choose AMDL as a vendor of choice.
16. CHANNEL PARTNERS IN INDIA
www.arts.net.in
Incorporated in 1995 Arts Agencies a vibrant and dynamic marketing
company strives to provide a complete suite of solutions to its
customers in the areas of Analog, Digital, RF & Embedded Design
Analog Digital Design.
Take care of Aldec product distribution in Defense
organizations like DRDO Labs
Labs.
