1. 1 / 22
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2. www.thalesgroup.com
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
FlexTiles
www.flextiles.eu
Duration: 36 months
Fabrice Lemonnier, DATE 2012
Research & Technology

3. 3 / 22
low volume
Cognitive radio
www.flextiles.eu
low power consumption
Embedded Real-Time Applications
Smart camera
UAV
Fault-tolerance
Time To Market
adaptable product line
Adapt to environment  dynamicity, flexibility & dependability
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Industrial issues
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4. 4 / 22 Challenges
address increasing application increase software development
dynamicity productivity of manycore
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-using self-adaptive capabilities -reduce Time to Market
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-reuse of legacy software
-reuse of hardware IPs.
increase accessibility to increase energy efficiency
manycore technologies
-for embedded systems
-propose a European alternative on
the worldwide market of this -andHigh-Performance Computing
technology (HPC) systems.
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5. 5 / 22 Objectives of the project
1) develop a heterogeneous manycore based on available IPs
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definition of generic interfaces
2) improve programming efficiency of heterogeneous
manycores
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3) self-adaptation
thanks to virtualisation layer
4) develop a dynamic reconfigurable technology
pre-emption and relocation capabilities.
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6. 6 / 22 Other Projects
Existing manycores provide static allocation and sheduling
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• TILE-Gx™ 8000 from Tilera (16 to 100 cores)
• MPPA® from Kalray (256 to 1024 cores)
• PicoArray from Picochip (248 cores)
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• FlexTiles (1 to thousands of cores)
Projects:
reconfigurable inside
Programmability
FlexTiles
Tsar Mosart
ADAM
Apple-Core
Morpheus
Aether
ReconOS
FOSFOR
Hardware Flexibility / dynamicity
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7. 7 / 22 1) develop a heterogeneous manycore system on a chip
Homogeneous
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GPP Node GPP Node GPP Node DDR Ctrl. I/O
GPP nodes
NI NI NI NI NI
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Generic
NoC
Interfaces
NI NI NI NI
AI AI AI Config. Ctrl.
Heterogeneous
accelerators DSP Dedicated Dedicated
Node Accelerator Accelerator
nodes Node Node
eFPGA Domain (Reconfigurable
www.flextiles.eu HW acc.)

8. 8 / 22
GPP
DSP nodes
eFPGA nodes
Slave Nodes
Master Nodes
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data
DMA
requests
DMA
NI
NI
NoC
GPP Node
control
/ status
node
accelerator
acc
requests
Accelerator Interface (AI)
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1) Execution model
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9. 9 / 22 2) programming efficiency of heterogeneous manycores
Application
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Parallelisation, partioning
toolchain Compilation Synthesis, P&R
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relocatable binary code relocatable bitstream
Operating Library API
Virtualisation ACTION
operating layer
library Kernel Resource
Monitoring & MONITORING DIAGNOSIS
O = F(L)
Allocation SYSTEM
Hardware Abstraction Layer API
heterogenous Hardware Abstraction Layer
manycore
Hardware Nodes
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10. 10 / 22 3) self-adaptation: virtualization layer
ACTION
Mapping
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MONITORING DIAGNOSIS
O = F(L)
SYSTEM
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Accelerator/Virtual Code
GPP Node GPP Node GPP Node DDR Ctrl. I/O
NI NI NI NI NI
NoC
Dynamic
allocation / binding
NI NI NI NI
AI AI AI Config. Ctrl.
DSP Dedicated Dedicated
Node Accelerator Accelerator
Node Node
eFPGA Domain (Reconfigurable HW acc.)
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11. 11 / 22
www.flextiles.eu
Tile
Tile
Tile
Tile
Tile
Tile
Tile
Homogeneous manycore
Tile
FlexTiles: a 3D stacked chip
Tile
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4) develop a new dynamic reconfigurable technology
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12. 12 / 22
Homogeneous manycore
www.flextiles.eu
Tile
Tile
NoC
Tile
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
Two layers communicating through one or several NoCs
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4) develop a new dynamic reconfigurable technology
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13. 13 / 22
NoC
Homogeneous manycore
www.flextiles.eu
Tile
Tile
Tile
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
3D stacked reconfigurable layer
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
4) develop a new dynamic reconfigurable technology
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14. 14 / 22
NoC
Homogeneous manycore
www.flextiles.eu
3D stacked reconfigurable layer
Tile
Tile
Tile
Tile
Tile
Tile
Tile
Map Accelerated functions
FlexTiles: a 3D stack chip
Tile
Tile
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4) develop a new dynamic reconfigurable technology
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15. 15 / 22
NoC
Homogeneous manycore
www.flextiles.eu
3D stacked reconfigurable layer
Tile
Tile
Tile
Duplicate
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
4) develop a new dynamic reconfigurable technology
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16. 16 / 22
NoC
Homogeneous manycore
www.flextiles.eu
3D stacked reconfigurable layer
Tile
Tile
Tile
Migrate
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
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4) develop a new dynamic reconfigurable technology
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17. 17 / 22 4) develop a new dynamic reconfigurable technology
thread1
thread3 thread1 thread2thread2 thread4
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API
I/O Acc1 Acc1 Acc3 Acc4 DDR ctrl
GPP GPP GPP GPP GPP GPP
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NoC
Dynamic allocation
Dynamic allocation
I/O
Acc1 thread1 thread2
Acc3
thread1 thread2 thread3 thread4
Acc1
Acc4 API
Tools for Tools for
parallelisation parallelisation
and mapping and mapping
Application
www.flextiles.eu

18. 18 / 22
GPP
shMEM
on chip
icache
dcache
dLMEM GPP
NI
www.flextiles.eu
DSP
iLMEM DSP
dLMEM DSP
NI
data
NOC
NOC
NOC
NOC
NOC
control
bitstream
test/debug
instruction
eFPGA
iLMEM eFPGA
dLMEM eFPGA
NI
+
NI
ctrl
DDR
chip
DDR
NoC QoS
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19. 19 / 22
low latency
highly scalable
packet switching
wormhole protocol
www.flextiles.eu
power efficient and dependable
between nodes: no global clock, no even local clock
GALS: asynchronous logic in nodes, local synchronous cores
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ANoC (CEA)
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20. 20 / 22
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Globally Synchronous with time slots
Contention free routing by construction
wormhole routing specified at design time
Guaranteed levels of services and performances
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AEtheral NoC (TUe)
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21. 21 / 22 Results
• Versatile accelerated multicore architecture
• SystemC simulator and FPGA demonstrators
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• Physical design of embedded reconfigurable technology
• To be implemented on a 3D stacked layer
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• HW and SW interfaces to address heterogenous manycores
• Create or use standards
• Virtualisation layer code, kernel
• Self adaptive
• Heterogeneous manycore Tool chain
• Design both multicore and accelerated functions at the same time
• Network selection according to required QoS
www.flextiles.eu

22. 22 / 22 8 partners in 5 countries Consortium and questions
Partners & Third Country Main scientific and
Party technical contributions
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THALES France Infrastructure and
applications
KIT Germany Virtualisation layer
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TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United FPGA Demonstrator
Kingdom
ACE Netherlands Parallelisation and
compilation Tools
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23. 23 / 22


www.flextiles.eu
Questions ?
Thank you for your attention
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8