1. Basic Processing Unit
V.Saranya
AP/CSE
Sri Vidya College of Engineering and
Technology,
Virudhunagar

2. Objective
Execution of Instructions.
Single Bus Organization of the Processor.
Multiple Bus Organization of the Processors.

3. Some Fundamental Concepts
 Processor (CPU): the active part of the
computer, which does all the work (data
manipulation and decision-making).
 Datapath: portion of the processor which
contains hardware necessary to perform all
operations required by the computer (the
brawn).
 Control: portion of the processor (also in
hardware) which tells the data path what needs
to be done (the brain).

4. Instruction
 Instruction execution Fetch
cycle:
Instruction
fetch, decode, execute Decode
.
 Fetch: fetch next Operand
Fetch
instruction (using
PC) from memory Execute
into IR.
Result
 Decode: decode the Store
instruction.
 Execute: execute
Next
Instruction
instruction.

5. Fetch
 Fetch: Fetch next instruction into IR
(Instruction Register).
 Assume each word is 4 bytes and each
instruction is stored in a word, and that
the memory is byte addressable.
 PC (Program Counter) contains address
of next instruction.
IR  [[PC]]
PC [PC] + 4

6. Single Bus Organization
Internal processor bus
Control signals
PC
...
Instruction decoder
Address line and control logic
MAR
Memory bus
MDR
Data line
IR
Y
Constant 4
RO
Select MUX
:
:
Add
A B R(n–1)
ALU control Sub
lines : ALU
Carry-in
XOR
TEMP
Z

7. Instruction Execution
 An instruction can be executed by performing one
or more of the following operations in some
specified sequence:
 Transfer a word of data from one register to
another or to the ALU (Arithmetic Logic Unit).
 Perform an arithmetic or a logic operation and
store the result in a register.
 Fetch the contents of a given memory location
and load them into a register.
 Store a word of data from a register into a given
memory location.

8. Register Transfer
 Register to register transfer:
 For each register Ri, two control signals:
 Riin used to load the data on the bus into the
register.
 Riout to place the register’s contents on the
bus.
 Example: To transfer contents of R1 to R4:
 Set R1out to 1. This places contents of R1 on
the bus.
 Set R4in to 1. This loads data from the
processor bus into R4.

9. Register Transfer (2)
Internal processor
bus
Riin
Yin
X
X
Ri
Y
Constant 4
X
Select MUX Riout
A B
ALU
Zin X
Z
X
Zout

10. Arithmetic/Logic Operation
Internal
processor bus
 ALU: Performs Riin
Yin
arithmetic and logic X
X
operations on its A
Ri
Y
and B inputs. Constant 4
X
 To perform
Riout
Select MUX
R3  [R1] + [R2]:
1. R1out, Yin A B
ALU
2. R2out, SelectY, A
dd, Zin Zin X
3. Zout, R3in
Z
X
Zout

11. Arithmetic/Logic Operation (2)
 If there are n operations, do we need n ALU
control lines?
 We could use encoding, which requires log2 n
control lines for n operations. However, this
will increase complexity and hardware
(additional decoder needed).
Add
A B
Sub
ALU control ALU
lines :
Carry-in
XOR

12. Reading a Word from Memory
 Move R3, (R2) /* R2  [[R1]]
1. MAR  [R2]
2. Start a Read operation on the memory bus
3. Wait for the MFC response from the memory
4. Load MDR from the memory bus
5. R3  [MDR]
 MDR has four control signals: MDRin, MDRout, MDRinE and
MDRoutE
Memory-bus data Internal processor
lines bus
MOVE R3, (R2) MDRinE MDRin
Control Signals… X X
R2out, MARin, Read. MDR
WMFC
MDRout, R3in X X
MDRoutE MDRout

13. Reading a Word from Memory (2)
 Move (R1), R2 /* R2  [[R1]]
 Sequence of control steps:
1. R1out, MARin, Read
2. R2out, MDRinE, WMFC
3. MDRout, R2in
 WMFC: Wait for arrival of MFC (Memory-Function-
Completed) signal.
 MFC: To accommodate variability in response time, the
processor waits until it receives an indication that the
Read/Write operation has been completed. The
addressed device sets MFC to 1 to indicate this.

14. Storing a Word in Memory
 Move R2, (R1) /* [R1]  [R2]
 Sequence of control steps:
1.R1out, MARin
2.R2out, MDRin, Write
3.MDRoutE, WMFC
4.R1in.

15. Example 2
• MOVE (R2), R1.
• MAR  [R2] R2out, MARin,
R1out, MDRin, Write
• MDR  [R1]
WMFC
MDRout, R2in

16. Executing a Complete Instruction
 Add (R3), R1 /* R1  [R1] + [[R3]]
 Adds the contents of a memory location pointed
to by R3 to register R1.
 Sequence of control steps: Steps 1 – 3:
1. PCout, MARin, Read, Select4, Add, ZinInstruction
fetch
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Z , R1 , End

17. Multiple-Bus Organization
 Single-bus structure: Control sequences are long as
only one data item can be transferred over the bus
in a clock cycle.
 Figure on next slide shows a three-bus structure.
 All registers are combined into a single block called
register file with three ports: 2 outputs allowing 2
registers to be accessed simultaneously and have
their contents put on buses A and B, and 1 input
allowing data on bus C to be loaded into a third
register.
 Buses A and B are used to transfer source operands
to the A and B inputs of ALU, and result transferred
to destination over bus C.

18. Multiple-Bus Organization (2)
Bus A Bus B Bus C Bus A Bus B Bus C
Incrementer
Instruction
decoder
PC
IR
Register file
MDR
Constant 4
MAR
MUX
A
ALU
R
B
Address line
Memory bus
Processor: Datapath and Control data lines

19. Multiple-Bus Organization (3)
 For the ALU, R=A (or R=B) means that its A (or B)
input is passed unmodified to bus C.
 Add R4, R5, R6 /* R6  [R4] + [R5]
 Adds the contents of R4 and R5 to R6.
 Sequence of control steps:
1. PCout, R=B, MARin, Read, IncPC
2. WMFC
3. MDRoutB, R=B, IRin
4. R4outA, R5outB, SelectA, Add, R6in, End