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Introduction to i.MX27 Multimedia Applications Processors ,[object Object]
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Key Features Performance •  CPU complex: 400 MHz at 1.45 V, 266 MHz at 1.2 V •  System: 133 MHz CPU Complex •  ARM926EJ-S 400 MHz core •  16 KB L1 I-Cache and D-Cache •  16-channel DMA •  ETM real-time debug •  Smart Speed switch Multimedia •  MPEG-4 H.263/H.264 D1 HW codec •  Pre and post processing •  High-speed CMOS sensor interface Technology •  90 nm CMOS •  Package: 404 balls, 0.65 mm pitch MAPBGA, 17 mm x 17 mm package
Key Features cont’d External Memory Interface (EMI) •  SDRAM 16/32-bit, 133 MHz •  DDR 16/32-bit, 266 MHz •  NAND flash 8/16-bit •  PSRAM support Connectivity •  10 and 100 Mbps Ethernet/IEEE® 802.3MAC •  USB OTG high speed, host x 2 •  3 x MMC/SD, Memory Stick-Pro™ •  PCMCIA/CF •  ATA-6 (HDD) interface •  Audio MUX •  IrDA, keypad, 1-wire •  Configurable SPI x 3, SSI/I2S x 2, UART x 6 Advanced Power Management •  Dynamic process temperature compensation (DPTC) •  Active well bias Security Control •  Crypto accelerator •  Electronically blown fuse box •  High-assurance boot •  Security controller with encrypted RAM storage •  Real-time OS/SW integrity checker
Multimedia Features ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Power Consumption for i.MX27 Device To address the continuing need to reduce power consumption, the following techniques are incorporated into the i.MX27 processor: ,[object Object],[object Object]
Block Diagram
i.MX27 Connectivity
ARM926 Core Platform ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ARM926EJ-S Interrupt Controller (AITC) The AITC performs the following functions: •  Supports up to 64 interrupt sources •  Supports fast and normal interrupts •  Selects normal or fast interrupt request for any interrupt source •  Indicates pending interrupt sources via a register for normal and fast interrupts •  Indicates highest priority interrupt number via register. (Can be used as a table index.) •  Independently can enable or disable any interrupt source •  Provides a mechanism for software to schedule an interrupt •  Supports up to 16 software controlled priority levels for normal interrupts and priority masking •  Can single-bit disable all normal interrupts and all fast interrupts. (Used in enabling of secure operations.)
Security Features ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Clock and Reset Module (CRM) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Power-Up Sequence ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
enhanced  Multimedia Accelerator Light (eMMA_lt) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Digital Audio Multiplexer (AUDMUX) ,[object Object],[object Object],[object Object],[object Object]
Multimedia Interface – CMOS Sensor Interface (CSI) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Video Codec ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Fast Ethernet Controller (FEC) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Direct Memory Access Controller (DMAC) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Application Example 1 – V2IP ,[object Object],i.MX27
Example 2 - IP Camera
Additional Resource ,[object Object],[object Object],[object Object],[object Object],[object Object],Newark Farnell

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Introduction to i.MX27 Multimedia Applications Processors

  • 1.
  • 2.
  • 3. Key Features Performance • CPU complex: 400 MHz at 1.45 V, 266 MHz at 1.2 V • System: 133 MHz CPU Complex • ARM926EJ-S 400 MHz core • 16 KB L1 I-Cache and D-Cache • 16-channel DMA • ETM real-time debug • Smart Speed switch Multimedia • MPEG-4 H.263/H.264 D1 HW codec • Pre and post processing • High-speed CMOS sensor interface Technology • 90 nm CMOS • Package: 404 balls, 0.65 mm pitch MAPBGA, 17 mm x 17 mm package
  • 4. Key Features cont’d External Memory Interface (EMI) • SDRAM 16/32-bit, 133 MHz • DDR 16/32-bit, 266 MHz • NAND flash 8/16-bit • PSRAM support Connectivity • 10 and 100 Mbps Ethernet/IEEE® 802.3MAC • USB OTG high speed, host x 2 • 3 x MMC/SD, Memory Stick-Pro™ • PCMCIA/CF • ATA-6 (HDD) interface • Audio MUX • IrDA, keypad, 1-wire • Configurable SPI x 3, SSI/I2S x 2, UART x 6 Advanced Power Management • Dynamic process temperature compensation (DPTC) • Active well bias Security Control • Crypto accelerator • Electronically blown fuse box • High-assurance boot • Security controller with encrypted RAM storage • Real-time OS/SW integrity checker
  • 5.
  • 6.
  • 9.
  • 10. ARM926EJ-S Interrupt Controller (AITC) The AITC performs the following functions: • Supports up to 64 interrupt sources • Supports fast and normal interrupts • Selects normal or fast interrupt request for any interrupt source • Indicates pending interrupt sources via a register for normal and fast interrupts • Indicates highest priority interrupt number via register. (Can be used as a table index.) • Independently can enable or disable any interrupt source • Provides a mechanism for software to schedule an interrupt • Supports up to 16 software controlled priority levels for normal interrupts and priority masking • Can single-bit disable all normal interrupts and all fast interrupts. (Used in enabling of secure operations.)
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21. Example 2 - IP Camera
  • 22.