GIET, Satya Prakash Das, VLSI PPT

1. VLSI

2. • What is VLSI?
– “Very Large Scale Integration”
• Single Transistor-----------------------------1958
• SSI – Small-Scale Integration (0-102)---1960
• MSI – Medium-Scale Integration (102-103)---1967
• LSI – Large-Scale Integration (103-105)---1972
• VLSI – Very Large-Scale Integration (105-107)---1978
• ULSI – Ultra Large-Scale Integration (>=107)---1989
• GSI _ Giant Scale Integration (>=109)---2000
*Where these are given as no of transistors.

3. ENIAC - The first electronic computer
(1946)
Digital Integrated Circuits Introduction © Prentice Hall 1995

4. Integration Level Trends
Obligatory historical Moore’s law plot

6. Example: Intel Processor Sizes
Silicon Process 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ
Technology
Intel386TM DX
Processor
Intel486TM DX
Processor
Pentium® Processor
Pentium® Pro &
Pentium® II Processors
Source: http://www.intel.com/

7. Why monolithic Integration?
•Less area/volume, compact size
•Less power consumption
•Less testing requirement at sys level
•Higher reliability, due to improved on chip
interconnects & elimination of soldered
joints.
•Higher speed, reduced int length & abs of
parasitic capacitance.
•Less cost and easy to handle

8. IC Products
• Processors
– CPU, DSP, Controllers
• Memory chips
– RAM, ROM, EEPROM
• Analog
– Mobile communication,
audio/video processing
• Programmable
– PLA, FPGA
• Embedded systems
– Used in cars, factories
– Network cards
• System-on-chip (SoC)
Images: amazon.com

9. What is an IC?
• It is a miniature, low cost electronic device
consisting of active and passive
components those are irreparably joined
together on a single crystal chip.

10. What is “CMOS VLSI”?
• MOS = Metal Oxide Semiconductor (This used
to mean a Metal gate over Oxide insulation)
• Now we use polycrystalline silicon which is
deposited on the surface of the chip as a gate.
We call this “poly” or just “red stuff” to
distinguish it from the body of the chip, the
substrate, which is a single crystal of silicon.
• We do use metal (aluminum) for
interconnection wires on the surface of the
chip.

11. • Integrated Circuits/MEMs
Hierarchy of various technology
Semiconductor process
Silicon GaAs
Bipolar Unipolar Bipolar Unipolar
ECL
NMOS PMOS
CMOS
TTL

12. • Selection of processing technology is a
trade off among Operating speed, Chip
area, Power dissipation.
• 1980------2mic.m tech-------64Kb per chip
• 1990------.5---------------------16Mb
• 1995------.25--------------------256Mb
• 2000------.18--------------------1Gb
• 2005------.15--------------------4Gb
• 2010------.08---------------------64Gb

13. VLSI Design Methodology
• Full custom Design style
• Semi custom Design style
• Frontend Designer
• Backend Designer

14. VLSI design flow--Y chart (D.GJASKI)

15. Top-down & bottom-up approach
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+
Digital Integrated Circuits Introduction © Prentice Hall 1995

16. FLOW CHART FOR VLSI DESIGN FLOW
Functional design
Fun verification
Logic design
Logic verification
Ckt design
Ckt verification

17. Layout design
Layout verification
Fabrication &
Testing

18. Chips
• Integrated circuits consist of:
– A small square or rectangular “die”, < 1mm thick
• Small die: 1.5 mm x 1.5 mm => 2.25 mm 2
• Large die: 15 mm x 15 mm => 225 mm 2
– Larger die sizes mean:
• More logic, memory
• Less volume
• Less yield
– Dies are made from silicon (substrate)
• Substrate provides mechanical support and
electrical common point

19. Advancements over the years
• © Intel 4004 • © Intel P4
Processor Processor
• Introduced in • Introduced in 2000
1971 • 40 Million
• 2300 Transistors Transistors
• 108 KHz Clock • 1.5GHz Clock

20. Intel 4004 Microprocessor

21. Intel Pentium (IV) Microprocessor

22. System Design Pyramid

23. Photolithography and
Patterning
• Photo-litho-graphy: latin: light-stone-writing
• Photolithography: an optical means for transferring patterns
onto a substrate.
• Patterns are first transferred to a photoresist layer.
•Typically a wafer is about 8-10 inches in diameter.
Individual ICs are placed inside it.

24. Photoresist is a liquid film that is spread out onto a
substrate, exposed with a desired pattern, and
developed into a selectively placed layer for subsequent
processing.
• Photolithography is a binary pattern transfer: there is
no gray-scale, color, nor depth to the image.

28. Steps
• Photo resist Coating (covering)
A light sensitive organic polymer (plastic)
• Mask/ Reticle formation
• Exposure to light (UV/X-RAY/E-BEAM)

31. WHAT IS A PHOTOMASK?
Photomasks are high precision plates containing microscopic
images of
electronic circuits. Photomasks are made from very flat pieces
of quartz or glass with a layer of chrome on one side. Etched
in the chrome is a portion of an electronic circuit
design. This circuit design on the mask is also called
geometry.

32. The Resist
The first step is to coat the Si/SiO2 wafer with a film of a
light sensitive material, called a resist.
Solvent Evaporates
A resist must also be capable of high fidelity recording of the
pattern (resolution) and durable enough to survive later
process steps

35. Photolithography
Energy
Mask + Aligner
Photoresist
Wafer
Energy - causes (photo)chemical reactions that modify resist
dissolution rate
Mask - blocks energy transmission to some areas of the resist
Aligner- aligns mask to previously exposed layers of the overall design
Resist - records the masked pattern of energy

36. Next Generation Lithography
In 1996, five technology options were proposed for the
130 nm gate length technology:
•X-ray proximity Lithography (XPL)
•Extreme Ultraviolet (EUV)
•Electron Projection Lithography (EPL)
•Ion Projection Lithography (IPL)
•Direct-write lithography (EBDW).
These options were referred to as the next generation
lithography.

38. MOSFET Design Rules
• Lambda based design Rule
• Micron Rule

39. Minimum width and Spacing
Layer Value
Poly 2L
Active 3L
N select 3L
Metal 3L

40. Stick Diagrams
Metal
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.

41. • Wiring Tracks
• A wiring track is the space required for a
wire
– 4 λ width, 4 λ spacing from neighbor = 8 λ
pitch
• Transistors also consume one wiring track

42. • Well spacing
• Wells must surround transistors by 6 λ
– Implies 12 λ between opposite transistor
flavors
– Leaves room for one wire track

43. Stick Diagrams
Basic Circuit Layout
VDD
VDD
X
X
x x x
x Stick
Diagra X
m
X
Gnd Gnd

44. Stick Diagrams
Layout Diagrams
VDD
VDD
X
X
x x x
x X
X
Gnd Gnd

45. Example: Inverter

46. MOSFET Arrays and AOI Gates
A B C
x y
A B C
y
x

47. Parallel Connected MOS Patterning
x x
A B
A B
X X X
y
y

48. Alternate Layout Strategy
x
x
X X
A B
A B
X X
y y

49. MOSFET Arrays and AOI Gates
NAND2 Layout
Vp Vp
X X X
a.b
Gnd
a.b
a b
X X
a b
Gnd

50. NOR2 Layout
Vp
Vp
X X
a+ b
a a +b
a b X
Gnd X X
b
Gnd

51. Stick Diagrams
Power
A Out
C
B
Ground

52. Cells, Libraries, and Hierarchical
Design
• Creation of a Cell Library
VDD
X X
x X x X
x x
X
X X
X X
Gnd

53. VDD
X
X X X
a xX
X
a.b
X
X X
X
a.b
b
Gnd

54. VDD
X
X X
x
X
a+b
a X
a +b
X X X X
b
Gnd

55. • Cell Placement
• System Hierarchy (MOSFET-Gates-F/Fs-
Registers-Networks-Systems)
• Floorplans and Interconnect Wiring
• Y= (# of Good Chips/Total No)*100%
• Y=Yield
• ‘Y’ depends on total area=A, and no of
defects=D,
− AD
• Y=e *100%

56. Interconnects
• Place and Route Algorithm.
• Wiring Delay
• td=kl2
• l=length of inter connect.
td