this ppt presents a brief information about testability and automatic test pattern generation used in making of CMOS circuits

1. DESIGN FOR TESTABILITY
AND AUTOMATIC TEST
PATTERN GENERATION
DILIP MATHURIA
M.TECH (VLSI)
160137004

2. OBJECTIVES
 What is DFT?
 Why we need DFT?
 DFT Methods
 Testing Economics
 Goal of DFT
 ATPG
 BIST
 Faults Models
 Stuck at Faults Model
 Path Sensitization

3. WHAT IS DFT?
 Design for testability (DFT) refers to those
design techniques that make test generation and
test application cost-effective.
 DFT consists of IC design techniques that add
testability features to a hardware product
design.
 The purpose of manufacturing tests is to
validate that the product hardware contains no
manufacturing defects that could adversely

4. WHY DESIGN FOR TESTABILITY?
Testability is a design characteristic that
influences various costs associated with
testing.
It allows for:
Device status to be determined
Isolation of faults
Reduce test time and cost

5. CONTROLLABILITY
Ability to establish a specific signal value at
each node by setting circuit’s inputs
Circuits typically difficult to control: decoders,
circuits with feedback, oscillators, clock
generators …

6. OBSERVABILITY
Ability to determine the signal value at any
node in a circuit by controlling the circuit’s
inputs and observing its output

7. PREDICTABILITY
Ability to obtain known output values in
response to given input stimuli
Factors affecting predictability
Initial state of circuit
Hazards

8. DIFFICULT TEST CASES
Sequential logic is more difficult to test than
combinational logic
Control logic is more difficult to test than data-
path logic
Random logic is more difficult to test than
structured bus-oriented designs
Asynchronous design is more difficult to test
than synchronous design

9. TESTING ECONOMICS
 Chips must be tested before they are assembled onto
PCBs, which, in turn, must be tested before they are
assembled into systems.
 The rule of ten:
 If a chip fault is not detected by chip testing, then
finding the fault costs 10 times as much at the PCB
level as at the chip level.
 Similarly, if a board fault is not found by PCB testing,
then finding the fault costs 10 times as much at the

10. GOAL OF DESIGN FOR TESTABILITY
(DFT)
Improve
Controllability
Observability
Predictability

11. DFT METHODS
DFT methods for digital
circuits:
Ad-hoc methods
Structured methods:
Scan
Partial Scan
Built-in self-test (BIST)

12. AD-HOC DFT METHODS
Good design practices learnt through experience are used as
guidelines:
Avoid asynchronous (unclocked) feedback
Make flip-flops initializable
Avoid redundant gates
Avoid large fan-in gates
Provide test control for difficult-to-control signals
Avoid gated clocks
Design reviews conducted by experts or design auditing
tools
Disadvantages of ad-hoc DFT methods:
Experts and tools not always available
Test generation is often manual with no guarantee of high fault
coverage

13. SCAN DESIGN
Circuit is designed using pre-specified design rules.
Test structure (hardware) is added to the verified design:
Add a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect to form
one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
Use only clocked D-type of flip-flops for all state variables
At least one PI pin must be available for test; more pins, if
available, can be used

14. BUILT-IN SELF-TEST
 Advances in microelectronics technology have
introduced a new paradigm in IC design: System-on-
Chip (SoC)
 Many systems are nowadays designed by embedding
predesigned and preverified complex functional blocks
(cores) into one single die
 Such a design style allows designers to reuse previous
designs and will lead to shorter time-to-market and
reduced cost
System-on-Chip
Embedded
DRAM
Int er f ace
Cont r ol
opmplex
cor e
UDL
gacy
cor e
DSP
cor e
Self - t est
cont r ol
49. 1
UDL
 SoC structure breakdown:
 10% UDL
 75% memory
 50% in-house cores
 60-70% soft cores

15. BIST TECHNIQUES
 BIST techniques are classified:
 on-line BIST - includes concurrent and non-concurrent techniques
 off-line BIST - includes functional and structural approaches
 On-line BIST - testing occurs during normal functional operation
 Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually
coding techniques or duplication and comparison are used
 Non-concurrent on-line BIST - testing is carried out while a system is in an idle state, often by
executing diagnostic software or firmware routines
 Off-line BIST - system is not in its normal working mode, Usually
 on-chip test generators and output response analysers or micro diagnostic routines
 Functional off-line BIST is based on a functional description of the Component Under Test
(CUT) and uses functional high-level fault models
 Structural off-line BIST is based on the structure of the CUT and uses structural fault models
(e.g. SAF)

16. GENERAL ARCHITECTURE OF BIST
BIST
Control Unit
Circuitry Under Test
CUT
Test Pattern Generation (TPG)
Test Response Analysis (TRA)
BIST components:
Test pattern generator (TPG)
Test response analyzer (TRA)
TPG & TRA are usually
implemented as linear
feedback shift registers
(LFSR)
Two widespread schemes:
test-per-scan
test-per-clock

17. BIST BENEFITS
Reduced testing and maintenance cost
Lower test generation cost
Reduced storage / maintenance of test patterns
Simpler and less expensive ATE
Can test many units in parallel
Shorter test application times
Can test at functional system speed

18. DRAWBACKS OF BIST
Additional pins and silicon area needed
Decreased reliability due to increased silicon area
Performance impact due to additional circuitry
Additional design time and cost

19. BOUNDARY SCAN
 An outline of a typical test procedure using a boundary scan is
as follows:
– A boundary-scan test instruction is shifted into the IR
through the TDI.
– The instruction is decoded by the decoder associated with
the IR to generate the required control signals so as to
properly configure the test logic.
– A test pattern is shifted into the selected data register
through the TDI and then applied to the logic to be tested.
– The test response is captured into some data register.
– The captured response is shifted out through the TDO
for observation and, at the same time, a new test pattern can
be scanned in through the TDI.

20. AUTOMATIC TEST PATTERN
GENERATION
Automatic test equipment (ATE) is computer-controlled equipment used in
the production testing of ICs (both at the wafer level and in packaged devices)
and PCBs.
Test patterns are applied to the CUT and the output responses are compared
to stored responses for the fault free circuit.
Generating effective test patterns efficiently for a digital circuit is thus the
goal of any Automatic-Test-Pattern- Generation (ATPG) system.
The effectiveness of ATPG is measured by the number of modeled defects, or
fault models, detectable and by the number of generated patterns.

21. TESTING PRINCIPLE

22. FAULT MODELS
Stuck-at fault model
Transistor faults
Bridging faults
Delay faults
• Delay faults can be classified as:
1) Gate delay fault
2) Transition fault
3) Hold Time fault
4) Slow/Small delay fault

23. 0
1
1
1
0
1/0
1/ 0
stuck-at-0
Fault-free ResponseTest Vector
Faulty Response
Assumptions:  Only one line is faulty.
 Faulty line permanently set to 0 or 1.
 Fault can be at an input or output of
a gate.
STUCK-AT FAULT MODEL
 In this model, one of the
signal lines in a circuit is
assumed to be stuck at
a fixed logic value,
regardless of what
inputs are supplied to
the circuit.

24. MULTIPLE STUCK-AT FAULTS
Several stuck-at faults occur at the same time
Important in high density circuits
For a circuit with k lines
There are 2k single stuck-at faults
There are 3k-1 multiple stuck-at faults
ATPG algorithms for multiple s-a-faults are
much more complex and not as well developed

25. WHY SINGLE STUCK-AT FAULTS?
 Complexity is greatly reduced.
Many different physical defects may be modeled by the same
logical single stuck-at fault.
 Single stuck-at fault is technology independent.
Can be applied to TTL, ECL, CMOS, etc.
 Single stuck-at fault is design-style independent.
Gate Arrays, Standard Cell, Custom VLSI
 Even when single stuck-at fault does not accurately model
some physical defects, the tests derived for these faults may
still be effective for these defects.
 Single stuck-at tests cover a large percentage of multiple
stuck-at faults.

26. TRANSISTOR FAULTS
This model is used to describe faults for CMOS logic gates. At transistor level,
a transistor maybe stuck-short or stuck-open.
In stuck-short, a transistor behaves as it is always conducts (or stuck-on), and
stuck-open is when a transistor never conducts current (or stuck-off). Stuck-
short will produce a short between VDD and VSS.
BRIDGING FAULTS
A short circuit between two signal lines is called bridging faults. Bridging to
VDD or VSS is equivalent to stuck at fault model.
If one driver dominates the other driver in a bridging situation, the dominant
driver forces the logic to the other one, in such case a dominant bridging fault
is used.

27. COMBINATIONAL ATPG
 The combinational ATPG method allows testing the individual
nodes (or flip-flops) of the logic circuit without being concerned
with the operation of the overall circuit.
 During test, a so-called scan-mode is enabled forcing all flip-
flops (FFs) to be connected in a simplified fashion, effectively
bypassing their interconnections as intended during normal
operation.
 This allows using a relatively simple vector matrix to quickly test
all the comprising FFs, as well as to trace failures to specific FFs.

28. SEQUENTIAL ATPG
Sequential-circuit ATPG searches for a sequence of test vectors to
detect a particular fault through the space of all possible test vector
sequences.
Even a simple stuck-at fault requires a sequence of vectors for
detection in a sequential circuit.
Due to the presence of memory elements, the controllability and
observability of the internal signals in a sequential circuit are in
general much more difficult than those in a combinational logic
circuit.

29. Fault Sensitization
Fault Propagation
Line Justification
PATH SENSITIZATION

30.  Try path f – h – k – L. This path is
blocked at j, since there is no way to
justify the 1 on i
1
0
D
D1
1
1
D
D
D
PATH SENSITIZATION

31. Try simultaneous paths f – h – k – L and
g – i – j – k – L. These paths blocked at k
because D-frontier (chain of D
or D) disappears
1
DD
D
D
D
1
1
1
PATH SENSITIZATION

32. Final try: path g – i – j – k – L – test found!
0
D
D D
1 D
D
1
0
1
PATH SENSITIZATION

33. THANK YOU!!!