Trixboxguide

Trixbox quickstart guide
1.0.0 Overview :

Trixbox is an end to end digital control system design tool to perform simulations, generate control
coefficients and control code that can be directly used with microprocessor. This tool is intended as a help to
generate the code for discrete (digitally) controlled power supplies/motor drives.

Trixbox is a web based app. Hence no downloads, no upgrades etc are required. It does not require
knowledge of advanced control system design techniques and allows the user to get a workable solution
quickly without trial and error and without dealing with complex equations.

Trixbox also allows users to simulate their own code while configuring the system (PWM
modulation) in almost every conceivable mode.

Having said that trixbox is no substitute for experience and physical insight that may be required on a case to
case basis. Trixbox is not traditional simulation software where circuits or systems are drawn and simulated to
the last nanosecond. It’s an end to end design tool which handles many (most common) modes and systems.
However every single case and quirk cannot
be handled. It is meant as an auxiliary to our consulting services.

Note: Trixbox works best in fire fox and google chrome. Internet Explorer is not supported and will crash.

2.0.0 Key Features:

1. Supports many topologies (presently all derived from the buck topology and boost topology)
2. Automatic generation of control coefficients
3. C Code generation for digital control system for fixed point DSC
4. Various control and system operation modes (VSI, CSI, DCM, CCM, VMC, CMC, PCMC)
5. Advanced control system design methods (description below)
6. User Programmable dynamic triggering strategy
7. System level simulation of user code interaction

2.0.1 Description of features

Trixbox works in 2 modes standard mode and user code mode

Is the standard mode end to end control system design takes place? Starting from physical system
level parameters the gains are calculated, plots are generated and C code I generated with
instructions to integrate the C files.

In the user code mode the user can write his/her own custom code, configure the system in a much
wider variety of ways such as variable period, valley current mode, dynamically change the on time, off
time etc.

In essence any generic switching pattern can be used to drive the system and the subsequent results
can be observed. In this mode only time domain simulation plots are generated.

The sample files are the same for both the modes. Some of the data contained in the sample files
which may be modified by the user may or may not be relevant. However it may be left as it is or
deleted.

2.1.0 Standard mode:

The following features are relevant for the standard mode and are described below.

2.1.1 Topologies supported

Various common topologies derived from the buck topology are supported. These are

1. Buck
2. Sync Buck
3. Push Pull
4. Full Bridge for inverters
5. Full Bridge DC DC converter
6. Phase Shift full bridge
7. Half bridge for inverter
8. Half bridge for DC DC
9. Current fed push pull
10. Boost
11. Synchronous Boost

By doing slight modifications, dynamics of topologies such as series and parallel resonant circuits
can also be simulated.

However the code needs to be modified to accommodate some more effects. (Needs

little customization)

Other dynamic systems such as various kinds of motors can also be simulated and code generated

• Servo motor drives (speed and position control) (DC, BLDC, PMSM and ACIM)
• Linear actuators /solenoids (needs little customization)

In addition in conjunction with the trixbox software customized solutions can be obtained for
following systems

(Simulation, control system design and fixed point or floating point microprocessor based code for
various operating mode for the following systems)

1. Buck topology (and derived topologies such as half bridge, full bridge, push pull, phase shift full
bridge, forward)
2. Boost topology (and derived systems)
3. Buck Boost topology (and derived systems such as Flyback)
4. LLC series and parallel resonant topologies
5. Servo motor drives (Speed and position control)
6. Power factor correction using various algorithms
7. BLDC, DC, AC induction, PMSM motor (censored and sensor less speed and position control)
8. Linear electromagnetic actuators
9. Electro capacitive motors and actuators

The complete list of projects and algorithms that we have experience is provided under services and
technology.

www.controltrix.com/service.html

www.controltrix.com/tech.html

2.1.2 Automatic generation of control coefficients

The control coefficients are generated algorithmically based on the user parameters. Various checks
are also performed to ensure that the coefficients will give desired performance.

2.1.3 C code generation

The C code for digital implementation is automatically generated by trixbox software. The C code and some
other relevant pieces can be easily combined to get a working code fairly quickly and easily.

The C code snippets that are generated are as follows

Preprocessing of ADC signals

• C code performing calculations
• Converting Q15 to Duty or phase values (modulation) for various topologies
• Definitions of various constants (# define)
• A readme file that describes how to combine the various code snippets

2.1.4 Modes supported

Various modes are supported for the relevant topologies. These are listed below

Conduction modes
1. Simulation and design for discontinuous current conduction mode in asynchronous topologies
2. Simulation and design for continuous current conduction mode
Source
1. Voltage source (where the objective is to control the output voltage)
2. Current source (where the objective is to control the inductor current)

Control modes

1. Voltage mode control
2. Average Current mode control
3. Peak Current mode control

2.1.5 Advanced mathematical models and simulation techniques

Trixbox uses advanced algorithms to ensure better performance for your system. Some of key advantages are

as follows

1. Models the physical reality better than the averaged models. Performs ideal switched simulation

2. Fast proprietary simulation compared to most traditional solvers such as RungeKutta based ones.

3. Code is executed and simulated in lock step (like actual system).

4. Handles many digital system related quirks like zero order hold, computational delays and deadtime.

5. Analytical averaged model frequency domain simulation. (No numerical instabilities and consequent
incomprehensible results) as compared to traditional simulation software.

2.1.6 User programmable triggering strategy

Triggering the ADC at the correct instant is an important aspect of all digitally controlled Power systems. Trixbox
allows the user to program the triggering strategy. The trigger point is thus calculated based on the user code.
In the standard mode the switching period is fixed. The program that the user needs to write to describe the
trigger point needs to be in PYTHON syntax.

Note: The syntax is mostly like C, except special care needs to be paid to indentation. Refer to following
section for the valid format. Also for security reasons, use of special symbols and string operations are
prohibited.

2.2.0 User code execution mode
The user code execution mode allows the user to try out any customized code, and how it will interact with
the entire system and look at the performance.
The user can configure the system in many ways.

Essentially limits on Ton, Toff and period and other limiting conditions may be put. Under these limiting
conditions, the user code is executed.

The user code should be written in python syntax. Many special symbols and keywords are not allowed in the
code for security reasons.

PYTHON is a strongly typed language. Special emphasis has to be made regarding indentation. It is
recommended that TAB is used for indenting the code.

Only time domain plots are executed when the system is in User code execution mode as (any non linear code
can also be put down by the user and frequency response will be invalid as the condition for Linear time
invariant system may get violated).

In some of the topologies when the circuit is reduced to the basic topology, the effective switching
frequency may be different (Usually two times). This has to be kept in mind when setting limits etc.

Such topologies are center tapped secondary side, current doublers secondary side, Full Bridge for inverter.
Other topology also needs correction.

2.2.1 Limiting modes

The user can configure the system into various limiting modes. The code that gets executed is restricted by
these modes. This allows the user to simulate variable on time, off time and PWM time.

List of modes is presented .Some modes are not mutually exclusive. There is considerable overlap

Fixed or variable frequency

1. Fixed Period or Fixed frequency mode: This is the typical mode where the period is configured and
remains fixed. On time and off time may change
2. Variable period or frequency mode

Peak Current and valley current

1. Peak current based Ton reset mode

Active state of the pwm is started as usual. As soon as the current hits a preset value, the PWM output is turned
inactive. When the Current is below a certain limit the state is active. When the current hits a certain limit, the
PWM is made inactive for the rest of
the period (or some other condition that again starts the timer).The peak current limit can be
programmatically set in every interrupt.
This operation is similar to cycle by cycle current limiting and peak current mode control and is also useful in
hysteresis mode

2. Valley current based Period set mode

The PWM runs as usual determined by perhaps other modes. As soon as the current goes below a specified
threshold, the period is terminated and a new switching cycle starts. This mode is useful for valley current
control mode and hysteresis based control.

In addition minimum and maximum limits may be placed on Ton, Toff and the period. These limits serve as
limiting conditions. These conditions may be enabled and disabled

These limiting conditions supersede any calculations that are made and take precedence. The enabling and
disabling of limits and specifying the limit values may be performed by setting the appropriate values in the
‘.xlsx’ file. (please refer to getting started section).

For e.g.

If the maximum Ton is set to a certain value and if the current does not hit the peak value, under normal
circumstances 100 % duty will be reached. However with a maximum Ton set, the on
time will be limited to that value.

3.0.0 Getting started

Trixbox is very easy to use. To start with, the user has to download a couple of files, modify them with their own
parameters and upload them.

3.1.0 Input:

The first file is a Excel (.xlsx) file with parameter values such as passive components, feedback network etc.
You may download a sample .xlsx file from under the help tab, modify the parameter values and save it as
.csv(comma delimited) file and upload in the designated space. The parameter description is provided in
Appendix 3.0

All parameters are not necessary and the order of the various parameters can also be changed. In fact
some of the parameters may be not applicable in some of the modes. It is advisable to start from a fresh
.xlsx file (found under the help tab) and modifies the relevant fields. You may even delete those which are
not required

The second (.txt) file input has a number of sections. The user may edit them based on the formats
specified. Each section begins with xxxx<Sectionname>start and ends with xxxx<Sectionname>stop

Anything written outside of the respective sections is ignored. Please do not write the keywords which specify
start and stop of a section anywhere else.

The operating conditions in .xlsx file represent the time varying quantities like desired voltage (Vref), Load
current (Io) , input voltage (Vin) for voltage source (where the primary control objective is output voltage).
The files are essentially excel files where the data can be specified in various formats. The formats are specified
in Appendix 1.0 at the end of this document.

These are required to perform time domain simulations.

The sections in .txt file are code snippets for dynamic triggering strategy. In a digital power control system the
choice of triggering the ADC (the point in the switching cycle the waveforms are sampled is very critical). This
piece of code is directly executed for simulation. Example code snippets are specified in Appendix 2.0 that
can be used for dynamic triggering.

Also the same file can be modified to incorporate user defined code.

In the user code mode the code also needs to be written as part of the ‘.txt’ file.

The specified format is presented in Appendix 4.0

Many parameters or sections in either .xlsx file may not be required for some particular operation. These
values may be left as they are in the sample files.

3.2.0 Output:

Once all the data has been entered, submit should be pressed. The plots may need to be refreshed as
browser may cache old data.

The tool generates the following output:

1. Bode plots for loop gain (phase margin and gain margin) for both analog and digital equivalent circuits.
2. Bode plot for closed loop (closed loop performance)

3. Disturbance rejection (inverse of output impedance for voltage source and output impedance for
current source) bode plot (the system performance when changes in load take place. It’s an absolute
metric. The higher the value the, more robust the system is. Details in later sections.
4. Time domain simulation plots include (Ripple content in voltage and current waveform,
average Output Voltage, Average inductor current, Average topside mosfet current in equivalent buck/boost
topology, Average bottomside mosfet current in equivalent buck/boost topology circuit), In the beta version,
these plots are limited in terms of number of points that can be simulated. The time domain simulations are
only performed
for the discrete (digital) power system.
5. All the results are available in the form of the download zip file which may be plotted using a
spreadsheet program such as Microsoft excel or goggle spreadsheets or open office. The data is all comma
separated values (x0, y0) (x1, y1) etc…

6. Automatically generated code files

i. .c code file, that needs to be integrated into your system by defining proper macros
ii. .h Parameter file with control coefficients
iii. Code for modulation (converting the output of the C code to duty etc) Needs to be copy pasted
iv. Readme with instructions
v. Log file to report any errors etc..

7. The download files include, the data for all the plots, c pseudo code files (which have to be modified based
on your processor by adding macros and specific libraries for multiply etc).

8. A generated readme file with description for which c file (pseudo code) needs to be used in the
microcontroller. The readme file also describes some code snippets that needs to be copy pasted
into the c file. These code snippets are basically related to modulation strategies.
More code snippets for preprocessing current will be added in due course

9. Readme file and log file :
Please look at the readme file and log file. The readme file is dynamically generated based on the
system. A brief overview is presented for what you should be looking for:

The generated pseudo code is in controlcode.c
ii. The modulation pseudo code is in mod.c
iii. If secondary side modulation is required , the secondarydutygen.c has the code for
synchronous rectification
iv. The control coefficients are present in defs.h
v. Various output data are present in different files in the download.zip.

A description of the data in each of the filesoutputxx.txt is provided in the table below.

Plot Xaxis data ( Yaxis data ( 2nd
File num num 1st column) column) Plot description legend
Output xx.txt xx =
01,02,03…
output01.txt 1 log 10 (f) Gain in dB Loop gain bode plot [gain] Analog system loop
Frequency 20 log10 (gain) Vo(s)/Verr(s) for Voltage gain magnitude
(Hz) source
(primary control objective
output voltage)

Io(s)/Ierr(s) for Current
source
(primary control objective is
output current)

output02.txt 2 log 10 (f) Angle (degrees) Loop gain bode plot [phase] Analog system loop
Frequency Vo(s)/Verr(s) for Voltage gain phase
(Hz) source
output voltage)
source
output current)

output03.txt 1 log 10 (f) Gain in dB Loop gain bode plot [gain] Digital system loop
Frequency 20 log10 (gain) Vo(s)/Verr(s) for Voltage gain magnitude
(Hz) source
output voltage)
source
output current)

output04.txt 2 log 10 (f) Angle (degrees) Loop gain bode plot [phase] Digital system loop
Frequency Vo(s)/Verr(s) for Voltage gain phase
(Hz) source
output voltage)
source

output current)

output05.txt 3 log 10 (f) Gain in dB Closed Loop gain bode plot Closed loop Analog
Frequency 20 log10 (gain) [gain] gain
(Hz) Vo(s)/Vref(s) for Voltage magnitude
source
output voltage) Io(s)/Iref(s)
for Current

source
output current)

output06.txt 4 log 10 (f) Angle (degrees) Closed Loop gain bode plot Closed loop Analog
Frequency [phase] gain phase
(Hz) Vo(s)/Vref(s) for Voltage
source
output voltage)
Io(s)/Iref(s) for Current
source
output current)

output07.txt 3 log 10 (f) Gain in dB Closed Loop gain bode plot Closed loop digital
Frequency 20 log10 (gain) [gain] gain magnitude
source
output voltage) Io(s)/Iref(s)
for Current source

output current)

output08.txt 4 log 10 (f) Angle (degrees) Closed Loop gain bode plot Closed loop Digital
Frequency [phase] gain phase
source

output voltage)
Io(s)/Iref(s) for Current
source
output current)

output09.txt 5 log 10 (f) log(|Io(s)/Vo(s)|) for Disturbance rejection[gain] Analog system
Frequency voltage source disturbance
(Hz) (primary control Higher this value the stiffer rejection magnitude
objective output the stiffer and better the
voltage) system
log(|Io(s)/Vo(s)|) for voltage
source
log(|Vo(s)/Io(s)|) for (primary control objective
voltage source output voltage)
(primary control Also the inverse of output
objective output impedance
current) log(|Vo(s)/Io(s)|) for voltage
source
output current)
Output impedance

output10.txt 5 log 10 (f) log(|Io(s)/Vo(s)|) for Disturbance rejection[gain] Digital system
Frequency voltage source Higher this value the stiffer disturbance
(Hz) (primary control the stiffer and better the rejection
objective output system magnitude
voltage)
log(|Io(s)/Vo(s)|) for voltage
source
log(|Vo(s)/Io(s)|) for (primary control objective
voltage source output voltage)
(primary control Also the inverse of output
objective output impedance

current) log(|Vo(s)/Io(s)|) for voltage
source
output current)
Output impedance

output11.txt 6 Time (s) Inductor Current ripple Current ripple vs time
(delta IL) pk to pk (A)
output12.txt 7 Time (s) Output Voltage ripple Voltage ripple vs time
(delta Vo) pk to pk (V)
output13.txt 8 Time (s) Average output voltage Average voltage vs time
(V)
output14.txt 9 Time (s) Average inductor Average current vs time
current (A)
output15.txt 10 Time (s) Average Topside Average Topside Mosfet
Mosfet current (A). current vs time
(equivalent Buck/boost
ckt)
output16.txt 11 Time (s) Average Bottom Mosfet Average Bottomside Mosfet
current (A) current vs time
(equivalent Buck/boost
ckt)
output17.txt 12 Time (s) Rising current slope A/s Rising current slope vs time
output18.txt 13 Time (s) Falling current slope A/s Falling current slope vs time
output19.txt 14 Time (s) Peak current (A) Peak current vs time
output20.txt 15 Time (s) Valley current (A) Valley current vs time

4.0.0 Future additions
 Other converter topologies of the buck boost family
 Better UI
 Detailed Documentation

5.0.0 Appendix 1: Input file formats
Formats for simulation time domain series.

There are multiple formats in which the Signals like reference voltage Vref, output current Io etc can be
uploaded.

For some special waveforms like sine wave, square wave etc there is a templatized version where writing
only a few lines and uploading it will generate the correct waveform internally.

5.1.0 General rules

1. The first line specifies what type of wave is being generated. Sinewave, rectified sinewave, square
wave, triangle wave (also almost a sawtooth wave), an interpolated wave,
2. constant or a simple time vs voltage sequence can be generated in a periodic or non
3. periodic manner.
4. Instead of letting the user just upload time value pairs, some common functions like sine,
square etc have been provided which can be used in a parametric form.
5. Some assume a periodic wave needs to be generated. If a non periodic wave is required, enter a
non zero very small value for frequency such as 0.1 or 0.01 Hz.
6. The .xlsx file must be opened and entries must be entered in successive lines in the space
provided.
7. Save the file in .csv (comma delimited) format and upload it in the designated space.

8. The points generated will always be at the system sampling frequency used in simulation.
9. It assumes that changes in these variables time sequences always occur aligned to PWM edges.
The period is always the PWM period.
10. So if PWM period is 10us and 500 points need to be generated then the system will only
simulate for a duration of 5ms.
11. The number of points takes precedence over simulation time.

So even if the simulation time is larger than the time represented by number of points, the system
will truncate before that.

5.2.0 Formats:
5.2.1 Sine wave/rectified sinewave
To generate a sine wave, enter the values in the space provided under operating conditions in .xlsx file.
e.g. to generate a sine wave of 100 Hz, 10 amplitude, pi/2 rad phase lag , DC offset 0 and 500 points
enter the values in the space provided in a .xlsx file under operating conditions as below.

WAVEFORM (type / shape): sine
FREQUENCY (in Hz): 100
AMPLITUDE (in SI units): 10
PHASE (in radians): -1.159
DCOFFSET (in SI units): 0
NUMPOINTS (Number of points): 500

Note: Save the given .xlsx file in .csv (comma delimited) format before uploading.

e.g. to generate a rectified sine wave of 100 Hz, 10 amplitude, pi/2 rad phase lag , DC offset 0 and 500
points enter the values in the space provided in a .xlsx file under operating conditions as below.

WAVEFORM (type / shape): rectsine
PHASE (in radians): -1.159


5.2.2 Square Wave

To generate a square wave, enter the values in the space provided under operating conditions in .xlsx
file.
e.g. to generate a square wave of 100 Hz, 10 amplitude, phase advance by 0.001 s, DC offset 0, 500
points and 30% duty, enter the values in the space provided in a .xlsx file under operating conditions
as below.

WAVEFORM (type / shape): square
PHASE (in seconds): -1.159
DUTY (between 0 and 1): 0.3


5.2.3 Triangle Wave

To generate a triangular wave, enter the values in the space provided under operating conditions in
.xlsx file.
e.g. to generate a triangle wave of 100 Hz, 10 amplitude, phase advance by 0.001 s, DC offset 0, 500
points and 30% duty, enter the values in the space provided in a .xlsx file under operating conditions
as shown below. In this case the upward slope will be for 30% of the period and downward slope will
be for 70%.

WAVEFORM (type / shape): square
PHASE (in seconds): -1.159
DUTY (between 0 and 1): 0.3


5.2.4 Subsampled sequence

Subsample sequence allows you to generate interpolated waveforms while specifying only a few
points.

It basically performs parabolic interpolation between points, where the interpolation needs to be
disabled to generate discontinuous waveforms like steps and jagged ones.

e.g. To generate a non periodic ramp passing though (0, 1) and (1, 2) and (2, 3) enter the values in the
space provided under operating conditions in .xlsx file.
So instead of specifying many points, it will fit a curve through these 3 points and generate 500 points
based on the system sampling frequency.

WAVEFORM (type / shape): subsampled
FREQUENCY (in Hz): 0.01
Time:value:continuity: 0, 1, 1


5.2.5 Arbitrary wave periodically sampled as a time, value pair

To enter brute force time versus amplitude in the rawest form use this. With this any arbitrary
waveform can be entered but it is also the most cumbersome. You may use some spreadsheet
software and then copy the data to the .xlsx. To enter 100 Hz wave with arbitrary shape enter as
follows: The sampling period is still determined by the PWM period in data set 1 as given in general
instructions given above.

In this format no interpolation (curve fitting or smoothening) is performed. The user may still enter
time and value pair where time values may still be arbitrary.

So if sampling period is 100us and user enter the values in the space provided under operating
conditions in .xlsx file.

WAVEFORM (type / shape): simpleseq
Time:value:continuity: 0, 0
Time:value:continuity: 0.001, 1

So for the first 10 samples (time interval of 100us between successive samples) the value will be 0.

Next 30 samples the value will be 1.

Next 10 samples value will be 0.

This allows the user to not have to enter values for all possible data point. Without having to worry
about entering time as a multiple of PWM period. This considerably condenses the data that needs
to be entered especially for waveforms with significant flat areas such as 6 step.

e.g.

WAVEFORM (type / shape): simpleseq


5.2.6 Constant

To enter a constant, enter the values in the space provided under operating conditions in .xlsx
file.
E.g. To enter a constant of 10 amplitude and 500 points enter as follows.

WAVEFORM (type / shape): Constant


6.0.0 Appendix 2.0: Dynamic triggering strategy
Use itrig variable when referring to current loop. Use

vtrig variable when referring to voltage loop.

The syntax of the code should be like python language.

Indentation is especially important in python. Always use tab for indentation.

Any complex code may be written to accommodate triggering strategy.

However string operations and many special characters are not allowed to be used.

In the sample file a dummy code is already present. This may be modified as required
<tab>itrig = 0

Some rudimentary error reporting has been implemented. The errors get written in the log file.

All units here are based on Q15 or fraction scale.

32767 is 100 % or full effective period. (For topologies

Default value is 0.

Sample code for dynamic triggering e.g. 1: This will trigger at the start of the PWM period

<Tab>itrig = 0

Sample code for dynamic triggering e.g. 2: The below code will trigger @ 25 % of the period.

<Tab>itrig = 8191

Sample code for dynamic triggering e.g. 3: The below code will trigger at 50% of the duty

<Tab>itrig = Duty/2

Sample code for dynamic triggering e.g. 4: The following code will trigger at 10% of period before
the duty. If duty is 50 % then the below code will trigger at 40%.

itrig = Duty – 3276

Similarly for changing voltage loop triggering use vtrig

instead of itrig.

7.0.0 Appendix 3.0: Parameter description

The following section describes all the parameters that are used to describe the system and are
present in the ..xlsx file

All values should be input in standard metric/SI units such as Henries, farads, seconds, ohms, volts,
amperes and watts

Not all parameters may be required in all situations. The original values which are the default may
be left as they are if they are not required.

7.1.0 TOPOLOGY AND SYSTEM DESCRIPTION

The following section describes the various topology specific parameters that are used
to specify the system

7.1.1 Primary topology PRMRY_TPLGY

Select the topology on the primary side.

Enter the respective number in the .xlsx file in respective place

Reserved 0
Buck 1
Synchronous 2
Push pull 3
4
Full bridge (for inverter)
Full bridge (for DC DC) 5
Half Bridge for inverter 6
Phase Shift Full Bridge 7
Forward 8
Series resonant xx(not supported in beta version)* 9xx
Half Bridge (for DCDC) 10
Current fed push pull 11
Boost 0 (in boost family mode)
Synchronous Boost 1 (in boost family mode)

7.1.2 Secondary topology SCNDRY_TPLGY

Select the topology on the secondary side.
For non isolated converters select not applicable.


Center tap rectifier 0
Current Doubler rectifier 1
Centre tap Synchronous rectifier 2
Current Doubler Synchronous rectifier 3
Voltage Doubler half bridge rectifier 4
Full bridge rectifier 5
Not applicable (N/A) -1

7.1.3 Primary control objective PRMY_CNTRL_OBJ

Select primary control objective. If the goal is to control output voltage (irrespective of load
current) select output voltage. If the goal is to control the output current (where the output voltage
is determined by external factors).


output voltage 0

output current 1

7.1.4 Secondary control objective SCNDRY_CNTRL_OBJ

Select Secondary control objective.
E.g. usage Power factor correction output voltage. Not applicable in beta version.


Output voltage 0
Output current 1
Not applicable -1

7.1.5 Control mode CONTROL_MODE

Select Control strategy. Voltage mode control if only voltage feedback is taken. Peak current mode if
comparator action is used to limit Duty. Refer standard texts on the above. For Current source
converters (where primary control objective is current) only average current mode is valid.


Voltage mode control 0
Average current mode control 1
Peak current mode control 2

7.1.6 Transformer turn ratio TURNS_RATIO

A transformer is used in topologies like push pull, forward etc. Enter the turn ratio primary to
secondary.

E.g. If primary number of turns is 10 and secondary is 4 then enter 10/4 = 2.5 * Note: For center tap
configuration on the secondary side, the turn ratio to be entered is ratio of primary side to turns in
one of the legs of the secondary side.

7.1.7 Parallel modules or interleaved phases NUM_PAR_PHASES

In many topologies there are multiple phases running in parallel. Enter the number of parallel
modules or phases.

These phases must have a common input as well as common output point.

7.2.0 PASSIVE COMPONENTS

The following section describes various passive components in the system

7.2.1 Nominal value of inductance INDUCTANCE

If there are multiple paralleled modules / inductors enter the per phase inductance. If the secondary
side is current doubler circuit in some converters like Full Bridge, push pull etc, then only put the
value of inductance of one of the phases. Does not support inductor saturation in beta release. For
current fed push pull topology, enter the primary side inductance

7.2.2 Output capacitance CAPACITANCE

The total output capacitance in the L-C plant. If multiple phases are present then enter the total
capacitance at the point of load.

7.2.3 Lumped series resistance LSR

The Lumped series resistance needs to be measured for the system using the following steps

1. Provide constant duty such that output voltage is near operating point voltage for DC –DC
application.

2. Slowly increase load while measuring output voltage.

3. The output voltage will droop with increasing load.

4. The V vs I slope provide the lumped resistance.
Refer documentation for more details

7.2.4 Equivalent series resistance ESR

If multiple equivalent capacitors are present in the output. Enter value ESR/n where n is the
number of capacitors.

7.3.0 INPUT VOLTAGE

The following sections describes the min and max input voltages

7.3.1 Maximum input voltage VIN_MAX

Max input voltage allowed by the converter before it enters over voltage protection

7.3.2 Nominal input voltage VIN

The generated code can handle wide range of input voltages but specify nominal input voltage. E.g. If
allowed input voltage is 36-75 V then enter 55 which is somewhere in between.

7.3.3 Minimum input voltage VIN_MIN
Minimum input voltage where the system is expected to operate reliably without entering under
voltage protection

7.4.0 DSP CONFIG PARAMETERS

DSP configuration specific parameters

7.4.1 PWM switching frequency in Hz PWM_FREQ

7.4.2 PWM clock frequency PWM_CLK_FREQ

PWM clock frequency determines the resolution of the PWM and plays a very important role in
quantization

7.4.3 Voltage loop execution rate in Hz VLOOP_INTFREQ

The rate at which the voltage loops code is executed.

7.4.4 Current loop execution rate in Hz ILOOP_INTFREQ

The rate at which the current loop code is executed.

7.4.5 Deadtime as a fraction of PWM Period DEADTIME_FRACTION

Dead time for synchronous converters.

E.g. if deadtime is 1 us and period is 10 us then enter 1/10 =0.1. Enter a small value like 0.001 if not
using deadtime.

7.5.0 COMPUTATION DELAY

Computational delays to be modeled in the analysis is provided here

7.5.1 Computational delay of the innermost loop in s INNR_LOOP_DLY

The inner most loop, in current mode control is current loop, in voltage mode control or peak current
mode control it is the voltage loop. The time between signals is sampled and duty ratio to change is
captured in this parameter. Should be less than the relevant interrupt period / or relevant execution
loop

For e.g. PWM switching period is 10 us , The sampling for feedback takes place @ 1us and the duty is
updated at the end of the period then enter 9us.(Time between sampling and actual updating of
duty). This parameter is used only for generation of bode plots.

Typical values could be about half of the interrupt period or execution period when the
triggering or ADC sampling is performed properly.

Worst case scenario could be 1 interrupt period.

The delay is determined in real time for simulation purposes.

7.5.2 Computational delay of the outer loop in s OUTR_LOOP_DLY

The outer most loop, in average current mode control it is voltage loop. The time between signals is
sampled and duty ratio to change is captured in this parameter. Should be less than the relevant
interrupt period / or relevant execution loop

For e.g. PWM switching period is 10 us, The sampling for feedback takes place @ 1us and the duty is
updated at the end of the period then enter 9us.
(Time between sampling and actual updating of duty). For other cases it is not relevant. This entry
should be less than the relevant interrupt period.

This parameter is used only for generation of bode plots.

Typical values could be about half of the interrupt period or execution period when the
triggering or ADC sampling is performed properly.

Worst case scenario could be 1 interrupt period.

The delay is determined in real time for simulation purposes.

7.6.0 ADC AND PWM INTERFACE PARAMETERS

7.6.1 Voltage feedback cutoff frequency VFBK_BW

The voltage feedback circuit will have a finite bandwidth. Voltage can only be measured reliably
without attenuation up to certain frequencies this effects the simulation and calculation of gains.
Disabled in beta version.

7.6.2 Manipulator bandwidth of the system MANIP_BW

Limited implementation in beta version. Should be less than or equal to PWM frequency.

This factor decides how fast the manipulated input (e.g. steering wheel in a car) can be made to move.
For most buck converter using switch based drives, it is about the PWM frequency used.

However for some topologies like LLC resonant, where the transformer output is connected to
a bulk capacitor, the rate of change of applied voltage to the equivalent L-C plant is determine

by the transformer + capacitor circuit. Hence it becomes very critical when designing control

system.

It needs to be measured experimentally:

1. Give a step change in the manipulated input. Manipulated signal = (Drive signal such as duty ratio,
reference in peak current mode and period in LLC resonant circuit)

2. The output voltage is then measured.

3. By using manipulator BW = 1/2/π/τ where τ is the time taken to reach 60 % of the change in the
voltage applied to the LC plant

For e.g. consider an LLC circuit

The system is controlled by changing the frequency or period of the PWM. Suppose the period is
changed from 5 to 4.5 micro seconds as a step change suddenly. The resulting voltage on the
capacitor bank on the secondary side also changes.

The voltage applied to the LC plant at the output (Not the LLC impedance on the primary side) is the
voltage across the capacitor bank after the rectifier on the secondary side. If the voltage changes
from 4.5 V to a final value of 5 V in 1ms then, on the scope measure the time taken by the system to
reach 0.63* (5 - 4.5) = 0.325 V change from the initial level.

Suppose this time is found to be 700 us Then the manipulator bandwidth is given by
1/2/π/700e-6 ~ 250Hz.

This is like your steering wheel. The system cannot respond any faster than the steering wheel can be
turned. If the steering wheel turns too slowly, it doesn’t matter how good the driver is.

In performing the control system design, low manipulator bandwidth is required to be handled.

7.6.3 Triggered or Average TRIG_OR_AVG

Indicates that the ADC feedback is triggered at a certain instant or the averaged quantity
(Significant R-C time constant feedback network is present) is used for current measurement.

Triggered 0

Average 1

7.7.0 DESIRED SPEC

7.7.1 Maximum allowable steady state voltage error
VERROR_STEADYSTATE_MAX

Suppose the voltage needs to be 5 V with +/- 1% regulation. Then, enter 5 *0.01 = 0.05 V. This is the
maximum steady state error that can be tolerated.

It cannot be less than 0.1% because the ADC resolution is fixed at 10 bits (~0.1 %).

Suppose the voltage needs to be 5 V with +/- 1% regulation. Then, enter 5 *0.01 = 0.05 V. This is the
maximum steady state error that can be tolerated.

It cannot be less than 0.1% because the ADC resolution is fixed at 10 bits (~0.1 %)

7.8.0 ADC

7.8.1 Base voltage for output voltage VOUT_BASE

Enter the base voltage for the output voltage when using 10 bit ADC, the amount of actual voltage
that will generate full range ADC readout (1023) in the microprocessor.

When there are offsets involved in the feedback path, then it can be defined as delta V / (1 unit
change in 10 bit ADC reading) * 1024

e.g. 12V reads 700 counts in ADC and no offsets are present in the feedback circuit then Enter
Vbase as 12/700*1024 = 17.55 V

If there is a 512 count offset. ( 0 V will still read as 512) and 12 V reads as 700

Delta V is 12 V

Delta ADC counts is (700 -512) = 188

Enter Vbase as 12/188*1023 = 60. 5 V

Do not enter 0

7.8.2 Base Current used to calculate all current quantities IBASE

Base current which is used to normalize all current quantities. Used in average current mode control
When using 10 bit ADC, the amount if actual voltage that will generate a full range ADC readout in the
microprocessor.

When there are offsets involved in the feedback path, then it can be defined as delta I /(1 unit change
in 10 bit ADC reading) * 1024

Suppose e.g. 12 A reads 700 counts in ADC and no offsets in the feedback ckt then, Enter base as
12/700*1024 = 17.55 V

If there is a 512 count offset. (0 A will still read as 512) and 12 A read 700 Delta I is 12A Delta

ADC counts is (700 -512) 188 Enter I base as 12/188*1023 = 60.5 A

I base may not be relevant for voltage mode control, yet enter some positive value. I base is also
used for peak current mode control.

For this mode, In the above calculations replace ADC with DAC counts. Presently works for 10 bit
DAC!! Do not enter zero even if it is N/A.

7.8.3 Base voltage for Input voltage VIN_BASE

Enter the base voltage for input voltage. The base voltage is defined as below. When using 10 bit ADC,
the amount of actual voltage that will generate a full range ADC readout (1023) in the microprocessor.

When there are offsets involved in the feedback path, then it can be defined as delta V /(1 unit change
in 10 bit ADC reading) * 1024

e.g. 12V reads 700 counts in ADC and no offsets are present in the feedback circuit then Enter
Vbase as 12/700*1024 = 17.55 V

If there is a 512 count offset. ( 0 V will still read as 512) and 12 V reads as 700
Delta V is 12 V

Delta ADC counts is (700 -512) = 188

Enter Vbase as 12/188*1023 = 60.5 V Do not

enter 0

7.8.4 Operating point output voltage in Discontinuous Conduction Mode
OP_VOUT

The control system when the system is in discontinuous conduction mode of operation (in
asynchronous converters) will be designed around this operating point.

The control system will behave as designed only around this point.

The farther the system state moves from this point, more and more the system will behave in a
different manner.

7.8.5 Operating point Duty ratio for Discontinuous Conduction Mode
OP_DUTY

Estimated operating point duty ratio in Discontinuous conduction mode (DCM) operation of
asynchronous converters.

Disabled in beta version. Enter some value between 0 and 1.

7.8.6 Operating point Current for discontinuous conduction mode
OP_CURRENT

The control system when the system is in Discontinuous conduction mode of operation (in
asynchronous converters) is designed around this operating point current.

The control system will behave as designed only around this point. The farther the system state
moves from this point, more and more the system will behave in a different manner.

7.9.0 DRIVE LIMITS

Parameters to limit the drive between maximum and minimum values

7.9.1 Maximum duty ratio
DUTY_MAX

The drive to the equivalent buck/boost converter will be limited to this number. Used to generate
code and time domain simulation. Enter a number between (0 and 1) to limit the drive.
DMax should be > DMin

7.9.2 Minimum duty ratio DUTY_MIN

The drive to the equivalent buck/boost converter will be limited to this number. Used to
generate code and time domain simulation.

Enter a number between (0 and 1) to limit the drive. DMax

should be > DMin

7.9.3 Maximum currentref I_MAX

The drive in peak current mode control to the equivalent buck/boost converter will be limited to this
number. Used to generate code and time domain simulation

Enter a number between (0 and 1) to limit the drive. DMax

should be > DMin

7.9.4 Minimum currentref I_MIN

The drive in peak current mode control to the equivalent buck/boost converter will be limited to this
number. Used to generate code and time domain simulation. Enter a number between (0 and 1) to
limit the drive. DMax should be > DMin

7.10.0 INITIAL VALUES

Initial values of state variables

7.10.1 Vo initial value VOUT_INIT

Initial value of output voltage for time domain simulation

7.10.2 IL initial value IL_INIT

Initial value of inductor current for time domain simulation

7.11.0 CONFIDENCE LEVELS OR ACCURACY

7.11.1 Confidence factor in voltage measurement VOUT_ACC

This parameter is called decoupling. The decoupling is performed for all converters operating in
continuous conduction mode of operation. For peak current mode control this is N/A. This factor is
used to judge the tolerance of the system in the simulation.

Practical values are 0.9 to 1.1. 1 is ideal case (in real systems it’s never so)

0.9 means that the estimated or measured value of voltage is only 90% of the actual voltage
1.1 means that the estimated or measured value of voltage is 110% of the actual voltage

7.11.2 Confidence factor in Equivalent series resistance and
capacitance TAU_CZ_ACC

The ESR and capacitance have a time constant that effects (complicates) the dynamics and limits the
system performance. It can be compensated if it is somewhat known. Enter 0.01 if it is almost
unknown, Enter 1 if it is perfectly known. Enter 0.8 if the estimated value is 20% less than actual value
Enter 1.2 if the estimated value is 20% more than actual value Practical values 0.7 to 0.9 or 1.1 to 1.3.

7.11.3 Confidence factor in Lumped resistance RP_ACC

The value of lumped resistance (which was experimentally measured) may be underestimating or
overestimate. This uncertainty is captured here Enter 1 if it is perfectly known. Enter 0.8 if the

estimate is 20 % less than the actual one Enter 1.2 if the estimate is 20 % more than the actual one.
Practical value may fall in the following ranges (0.7-0.9) and (1.1 to 1.3)

7.12.0 PLOTTING AND DATA VISUALIZATION

7.12.1 Number of points in the range (Fmin and F max) spaced logarithmically
BODE_NUM_POINTS

For the bode plot generation the data for the bode plots will be generated for approximately these
many instances. A typical number could be in the range of 100 to 300

7.12.2 Minimum frequency for bode plot generation BODE_FMIN

Minimum frequency or lower limit of bode plots

7.12.3 Maximum frequency for bode plot generation BODE_FMAX

Maximum frequency or upper limit of bode plots

7.13.0 SIMULATION
7.13.1 Simulation time in s SIM_TIME

Time for which the simulation will run. Enter less than 10000 PWM cycles for response in reasonable
time frame. e.g. for a converter operating @ 100 KHz frequency, we can enter 0.1 s Enter less than
400*switching frequency for beta version.

7.14.0 ROOTS EIGEN VALUES OR POLES

7.14.1 F1 Desired pole, eigenvalue or root of characteristic equation. F1 >F2 >F3
ROOT1

ROOT2

ROOT3

Guidelines in choosing the value of F1, F2 and F3

Keep F1 < 1/7th the sampling and the code execution frequency. F1 < 1/10th the sampling
frequency is even better

1. Keep separation between F1, F2 and F3 to account for parameter tolerances. A factor
of 2 to 3 or more between them would suffice e.g. 900,300, and 100

2. All frequencies F1, F2 and F3 should be different from one another
3. In some cases only 1 or 2 roots may be required. Even then enter some value different.
4. For voltage mode control for voltage source converter F1 becomes the cutoff
5. For current mode control for voltage source converter F2 becomes the voltage loop
bandwidth, crossover freq etc.
6. For peak current mode control F1 is voltage loop bandwidth, crossover frequency etc.
7. For current mode control for current source F1 is the current loop bandwidth,
crossover freq etc.
8. In some modes not all F1, F2 and F3 are required. The user may still enter them.

7.15.0 MODE PARAMETERS 1 = ENABLED and 0 =DISABLED
In the user code mode the following parameters are used

7.15.1 Enable/Disable fixed period modeFIXED_PERIOD

When this mode is enabled the period or switching frequency is always fixed. The user code may set
the duty as a fraction of this value. In this mode Ton + Toff (the time of PWM active
and inactive states) is always constant specified.

ENABLED 1
DISABLED 0

7.15.2 Enable/Disable Cycle by cycle peak current limit mode IPEAK_TON_RESET

When this mode is enabled the system enters cycle by cycle peak current limit mode. At the onset
of the period, the PWM is driven to active state as usual. When the current crosses a limit, (which
may be set dynamically and programmatically) the PWM is driven inactive where it remains till the
end of the PWM period. This mode may be operated with or without FIXED_PERIOD and

IVALLEY_TOFF_RESET.

ENABLED 1
DISABLED 0

7.15.3 Cycle by cycle valley current limit mode IVALLEY_TOFF_RESET

When this mode is enabled, the PWM period is reset whenever the valley current falls below a limit.
The limit may be changed programmatically and dynamically by the user code. When the event
occurs the PWM is driven to an active state. This mode works with and without enabling
FIXED_PERIOD.

ENABLED 1
DISABLED 0

7.16.0 LIMIT PARAMETERS 1= LIMIT and 0 =DISABLED

These parameters enable and disable the min and max values. If these parameters are enabled
then the respective time quantity is bounded. For e.g. if TONMAX is enabled, then TON will always be
less than Tonmax limit set next. Though user code may also do some software protection to limit
these values, Sometimes a hardware limit is desirable. The following parameters are mainly used for
protection purposes in real systems.

7.16.1 Enable PWM active state (Ton) minimum limit TONMIN
If enabled, will limit the minimum Ton (time of PWM active state) to TONMIN_VAL.

ENABLED 1

DISABLED 0

7.16.2 Enable PWM active state (Ton) maximum limit TONMAX

If enabled, will limit the minimum Ton (PWM active state) to TONMAX_VAL

ENABLED 1
DISABLED 0

7.16.3 Enable PWM inactive state (Toff) minimum limit TOFFMIN

If enabled, will limit the minimum Toff (PWM inactive state) to TOFFMIN_VAL

ENABLED 1
DISABLED 0

7.16.4 Enable PWM inactive state (Toff) maximum limit TOFFMAX

If enabled, will limit the maximum Toff (PWM inactive state) to TOFFMAX_VAL

ENABLED 1
DISABLED 0

7.16.5 Enable PWM period (Tpwm) minimum limit TPWMMIN

If enabled, will limit the minimum Tpwm (PWM period) to TPWMMIN_VAL. Only valid when
FIXED_PERIOD is DISABLED.

ENABLED 1
DISABLED 0

7.16.6 Enable PWM period (Tpwm) maximum limit TPWMMAX

If enabled, will limit the maximum Tpwm (PWM period) to TPWMMAX_VAL. Only valid when
FIXED_PERIOD is DISABLED.

ENABLED 1
DISABLED 0

7.17.0 LIMITING VALUES

The following parameters allows the user to specify the limits on Ton, Toff and Tpwm. These values
become relevant when the respective LIMIT parameters are enabled. All values are in seconds.
These limits are typically relevant for safety and protection of the system. They only come into
effect when the corresponding LIMIT parameter is ENABLED.

7.17.1 Lower limit of Ton TONMIN_VAL
7.17.2 Upper limit of Ton TONMAX_VAL
7.17.3 Lower limit of Toff TOFFMIN_VAL
7.17.4 Upper limit of Toff TOFFMAX_VAL
7.17.5 Lower limit of Tpwm TPWMMIN_VAL
7.17.6 Upper limit of Tpwm TPWMMAX_VAL

7.18.0 ADC AND INTERFACE PARAMETERS

These are required to simulate the effect of quantization due to ADC bit resolution

7.18.1 Digital to analog converter/comparator input DAC_FULLRANGE

Full range counts of the DAC used for comparing in peak and valley current mode. For 10 bit it is 1024
and so and so forth. Essentially in peak current and valley current mode, the reference has to be said
programmatically. The reference number (in software) needs to be converted to a analog signal by a
digital to analog convertor for cycle by cycle limit. This parameter captures the resolution of the DAC.

7.18.2 Analog digital convertor full range ADC_FULLRANGE

Full range counts of the ADC used for sampling feedback signals. For 10 bit ADC it is 1024 and so and
so forth. In any digital control system, the analog feedback has to be sampled and converted into
digital value. The resolution of the sampling process is governed by this parameter.

8.0.0 Appendix 4.0

8.1.0 User code format (Only relevant for user code simulation mode)

In the user code mode, the user can simulate his own code. The following section describes the code
format.

The code has to follow PYTHON syntax

Some key features are as follows

Python is a strongly typed language which means that indentation (space at the start of each line is
very critical)

The code has to be properly indented.

The code should not contain special characters such as ; ‘ ,” .characters such as ‘[‘ and ‘]’
square brackets are allowed

The code should be a mathematical code. No string or shell utility based operations are allowed

The only variables allowed are Vrbl[0],Vrbl[1] and so on till Vrbl[200]. Vrbl is

an array of size 200.

The user code is essentially a function that gets called every interrupt.

In conjunction with the physical system model, the entire system is thus simulated.

In the PYTHON programming language, variables have local scope by default. So any variable stored will be
wiped off every time the function is called. Hence it is impossible to implement anything with memory within
these rules. Therefore an array Vrbl is passed to the function. Any values stored in the Vrbl array remains as it
is next time the function is called.

The code structure is typically as follows

The various real world signal feedback are copied into local variables. User code

where various calculations etc may be performed.

Finally the outputs are dumped into another set of variables which are returned by the function to
perform simulation.

An example code is provided here

<tab> Vrbl[1] = 3000

<tab> Toncounts = Vrbl[1]

<tab> Toffcounts = 6700

<tab> Tpwmcounts= 10000

<tab> DutyQ15 = 10000

<tab> Ipkrefcounts = 0

<tab> Ivlrefcounts = 0

<tab> ilooptrigQ15 = 0

<tab> vlooptrigQ15 = 0

The variables which are returned such as ‘Toncounts’ , ’Toffcounts’ automatically get declared when
they are called unlike a typical C implementation. Hence these assignment statements before return
such as

Toncounts = 1000 etc are critical.

The right hand side of the assignment statement may change based on user desire, but the left hand
side of the = sign should remain as they are.

Essentially all the user has to write the code, and get the numbers into a set of variables such as
Vrbl[0] ,Vrbl[1]…

Then these values may be assigned to the return group of variables like

Toncounts etc.

The system should be handling any valid user code under the framework defined for usercode.

8.2.0 Description of return group of variables

The following is the list of return variables and their description.

8.2.1 Toncounts :The on time Ton in counts. E.g. if Ton is 1us and PWM resolution is 1ns then
Toncounts will be 1000.

Toncounts is at the same scale as duty registers such PDCx in microchip processors
dspic33fjxxgsxxx

8.2.2 Toffcounts :The off time Toff in counts.

E.g. if Toff is 1us and PWM resolution is onces then Toffcounts will be 1000.

Toffcounts is at the same scale as duty register.

Toffcounts is at the same scale as duty registers such PDCx in microchip processors
dspic33fjxxgsxxx

8.2.3 Tpwmcounts :The time period in counts

E.g. if Toff is 1us and PWM resolution is 1ns then Toffcounts will be 1000.

Toffcounts is at the same scale as period register.

8.2.4 DutyQ15 : Duty value as a fraction expressed in Q15 format.

E.g. If duty ratio needs to be 0.5 then DutyQ15 will be 16383

8.2.5 Ipkrefcounts : Peak current value as counts in the system

When using mode that requires DAC based peak current, then the value used in DAC register

E.g. If 1A corresponds to 1024 counts in user hardware system, then to enter 0.5 A as the peak limit
the value should be 512

8.2.6 Ivlrefcounts : Valley current value as counts in the system

When using mode that requires DAC based valley current, then the value used in DAC register. E.g. If 1A

corresponds to 1024 counts in user hardware system, then to enter 0.5 A as the valley
Limit the value should be 512.

8.2.7 ilooptrigQ15 : Trigger value as a fraction of period for current sampling

The ADC for current related quantities are triggered and measured at this instant. It is
expressed as a fraction of the period Q15 format.

E.g. suppose the current needs to be triggered at 10 % of the period (Tpwm value). Then this variable
should be round (32768 * 0.1) = 3277

8.2.8 vlooptrigQ15 : Trigger value as a fraction of period for voltage sampling

The ADC for voltage related quantities are triggered and measured at this instant. It is
expressed as a fraction of the period Q15 format.

E.g. suppose the voltage needs to be triggered at 10 % of the period (Tpwm value). Then this variable
should be round (32768 * 0.1) = 3277

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