1. PHDL
PRINTED CIRCUIT BOARD
HARDWARE DESCRIPTION LANGUAGE
Brent Nelson, Brad Riching, Richard Black
Dept. of Electrical and Computer Engineering
Brigham Young University
October 25, 2011

2. Acknowledgements
• Pete Dudley – Sandia
– Ideas, motivation, and passion for this project
• Wes Landaker - Sandia
– Ideas, language design, compiler consulting
• Sandia Management
– Funding
2

3. Overview
• Who are we?
• What is PHDL? (a very short intro)
• Examples of PHDL
– Example board designs
• Language and grammar
• Tool flow
• What is PHDL? (more in-depth)
– Why textual input?
3

4. Who Are We?
• Dr. Brent Nelson
– Brigham Young University, Dept. of Electrical
and Computer Engineering
• Brad Riching
– MS Student in Computer Engineering
– BS in Electrical Engineering, Brigham Young
University, 2010
• Richard Black
– Undergraduate in Computer
Engineering, Brigham Young University
4

5. What is PHDL?
Schematic Capture PCB Layout
produces netlist interprets netlist
netlist
Bill of
Material,
other
ancillary
data
5

6. What is PHDL?
Schematic Capture PCB Layout
produces netlist interprets netlist
netlist
PHDL Bill of
PHDL compiler Material,
Source other
Code ancillary
data
6

7. What is PHDL? (a very short intro)
• An HDL for PC Boards
– Hardware Description Language
– For schematic entry (not layout)
• Similar to HDLs for IC and FPGA design
– Verilog, VHDL, etc.
• Goal == significantly increase:
– Productivity
– Collaboration
– Reuse
7

8. Why PHDL? (the short version)
1. Automation & productivity
– Iteration, hierarchy, ERC/DRC
2. Collaboration
– SCCS (source code control system)
• Shared repository for designs and part libraries
• Design versions, change tracking/documentation
• Diff, revert
3. Textual IDEs and tools
– Templates, auto-completion, search and
replace, library reuse
8

9. High Pin Count Devices - FPGAs
How much of this schematic is meaningful?
• Most circuit context
is absent.
• Many pins map to
devices on other
pages.
• Larger devices must
be split across
multiple pages
• Schematics don’t
scale well.
• HDL’s do!
9

10. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
10

11. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
11

12. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
12

13. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
13

14. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
14

15. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
15

16. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
16

17. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
17

18. Trivial Example
• We’ll illustrate some of the features of
PHDL with an example:
18

19. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
19

20. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
20

21. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
21

22. Creating a Design
device Resistor is
attr refPrefix = “R”;
attr pkg_type = “M0805”;
pin a = {1};
pin b = {2};
1
end device;
R?
M0805
2
22

23. Creating a Design
device Resistor is
attr refPrefix = “R”;
attr pkg_type = “M0805”;
pin a = {1};
pin b = {2};
1
end device;
R?
M0805
2
23

24. Creating a Design
device Resistor is
attr refPrefix = “R”;
attr pkg_type = “M0805”;
pin a = {1};
pin b = {2};
1
end device;
R?
M0805
2
24

25. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
25

26. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
26

27. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
27

28. Creating a Design
device SevenSeg is
attr refPrefix = “LD”;
attr pkg_type = “SA08-21”;
pin[1:8] segments =
LD?
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device; 2
15
13
11
5
3 4
14 12
10 17
SA08-21
28

29. Creating a Design
device SevenSeg is
attr refPrefix = “LD”;
attr pkg_type = “SA08-21”;
pin[1:8] segments =
LD?
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device; 2
15
13
11
5
3 4
14 12
10 17
SA08-21
29

30. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
30

31. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
31

32. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
32

33. Creating a Design
inst source of Battery is
pos = vcc;
neg = gnd;
end inst;
33

34. Creating a Design
inst source of Battery is
pos = vcc;
neg = gnd;
end inst;
34

35. Creating a Design
inst source of Battery is
pos = vcc;
neg = gnd;
end inst;
35

36. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
36

37. Creating a Design
inst segment of SevenSeg is
segments = segs;
anode = <vcc>;
end inst;
37

38. Creating a Design
inst segment of SevenSeg is
segments = segs;
anode = <vcc>;
end inst;
38

39. Creating a Design
inst segment of SevenSeg is
segments = segs;
anode = <vcc>;
end inst;
39

40. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
40

41. Creating a Design
inst(1:8) swArray of Switch is
combine.a = r2sw;
combine.b = segs;
end inst;
41

42. Creating a Design
inst(1:8) swArray of Switch is
combine.a = r2sw;
combine.b = segs;
end inst;
42

43. Creating a Design
inst(1:8) swArray of Switch is
combine.a = r2sw;
combine.b = segs;
end inst;
43

44. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
44

45. Creating a Design
inst(1:8) rArray of Resistor is
newattr value = “120”;
combine.a = r2sw;
each.b = gnd;
end inst;
45

46. Creating a Design
inst(1:8) rArray of Resistor is
newattr value = “120”;
combine.a = r2sw;
each.b = gnd;
end inst;
46

47. Creating a Design
inst(1:8) rArray of Resistor is
newattr value = “120”;
combine.a = r2sw;
each.b = gnd;
end inst;
47

48. Creating a Design
inst(1:8) rArray of Resistor is
newattr value = “120”;
combine.a = r2sw;
each.b = gnd;
end inst;
48

49. PHDL Example Design
design ssControl is net gnd, vcc;
device Resistor is net[1:8] segs, r2sw;
attr refPrefix = “R”; begin
attr pkg_type = “M0805”; inst source of Battery is
pin a = {1}; pos = vcc;
pin b = {2}; neg = gnd;
end device; end inst;
device Switch is inst segment of SevenSeg is
attr refPrefix = “SW”; segments = segs;
attr pkg_type = “MS243”; anode = <vcc>;
pin a = {1}; pin b = {2}; end inst;
end device; inst(1:8) swArray of Switch is
device Battery is combine.a = r2sw;
attr refPrefix = “G”; combine.b = segs;
attr pkg_type = “1V60R”; end inst;
attr value = “9V”; inst(1:8) rArray of Resistor is
pin pos = {2}; pin neg = {1}; newattr value = “120”;
end device; combine.a = r2sw;
device SevenSeg is each.b = gnd;
attr refPrefix = “LD”; end inst;
attr pkg_type = “MS243”; end design;
pin[1:8] segments =
{2,15,13,11, 5,3,14,10};
pin[1:3] anode = {4,12,17};
end device;
49

50. PHDL Example Design
design ssControl is
include “parts.phdl”;
net gnd, vcc;
net[1:8] segs, r2sw;
begin
inst source of Battery is
pos = vcc;
neg = gnd;
end inst;
inst segment of SevenSeg is
segments = segs;
anode = <vcc>;
end inst;
inst(1:8) swArray of Switch is
combine.a = r2sw;
combine.b = segs;
end inst;
inst(1:8) rArray of Resistor is
newattr value = “120”;
combine.a = r2sw;
each.b = gnd;
end inst;
end design;
50

51. How PHDL Works
~/user/brad/phdl/projects
$java phdl.Compile <file_name>.phdl [switches]
Abstract Syntax
Tree (AST)
PHDL Tree
Lexer Parser
source Parser
ANTLR framework
Command
line switches
• Netlist
• Bill of Materials
Analyzer / Output • Component List
Generator files • Layout Directions
• XML
51 • Tool-specific Scripts

52. Targeted Design Flows
EAGLE PCB
FPGA-based Motor
Controller - BYU
Mentor Graphics PADS
AD9739 High Speed DAC
FMC board – Pete Dudley
52

53. BYU Proof of Concept Board
FPGA-based motor controller (2-axes)
– Spartan3 400K 144-pin QFP implements:
• 32-bit position, vel. and accel. registers per axis
• Programmable PID filters, sampling intervals
• Trapezoidal velocity profile generators
• Packet router over RS232 to host PC application
– Supporting hardware
• 500+ CPR encoder feedback resolution
• PWM brushless and brushed motor drives
• The usual JTAG, Flash ROM, GPIO, etc.
53

54. Motor Controller Board
Single Axis Block Diagram
RS232 Host
Application
MOTOR DRIVERS
FPGA VHDL Hardware Outside
FPGA
54

55. Motor Controller Board
Final Layout in EAGLE
55

56. Motor Controller Board
Back From Manufacturing
56

57. Motor Controller Board
Assembled
Top Bottom

58. Motor Controller Board
First PCB Built using PHDL

59. Motor Controller Board
JTAG
Power Supply
12VDC IN: Motor Power
To 58VDC MAX
5V, 3.3V, 2.5
V, 1.2V
Brushless
FPGA / SRAM Drive (x2)
RS232
Brushed
Drive (x2)
Encoder
Feedback

60. Motor Controller Board
Host Application Interface (C#) Serial Config
Raw Data
Monitoring
Positioning
Commands
Reporting
Commands
Internal State
Registers
60

61. Automatic Device Generation
FPGA VHDL Location
Constraints PHDL Device Declaration
Design
library ieee;
device fpga is
#fpga.ucf attr refPrefix = "U";
use ieee.numeric_std.all;
use ieee.std_logic_1164.all; attr pkg_type = "tq144";
LOC “clk” = P52; attr mfgr = "XILINX";
entity fpga is
LOC “rst” = P40:
port( attr partNumber = "xc3s400-4tq144";
LOC “rxd” = P47;
clk : in std_logic;
LOC “rxd_a” = P41;
rst : in std_logic; // User I/O pins.
.
. pin clk = {P52};
-- RS232 serial ports pin rst = {P40};
.
rxd : in std_logic;
pin rxd = {P47};
txd : out std_logic;
rxd_a : in std_logic;
pin rxd_a = {P41};
txd_a : out std_logic; pin txd = {P46};
pin txd_a = {P44};
-- 12-bit DAC pin sclk = {P86};
sclk : out std_logic; pin sdata = {P87};
sync : out std_logic; pin sync = {P85};
sdata : out std_logic pin[7:0] data = {P23,P21,P20,P18...};
.
data : out .
std_logic_vector(7 downto 0)
.
. Synthesis, PAR, end;
.
. csv2phdl
);
end entity fpga;
61

62. Automatic Device Generation
Automated FPGA Device Declaration from HDL
HDL
csv2phdl PHDL
fpga.vhdl fpga.csv fpga.phdl Device
fpga.ucf Declaration
Synthesis, PAR
PHDL
Source Code
design myDes is
include “fpga.phdl”;
Revisions begin
…
end design;
62

63. Motor Controller Board
FPGA Instance
inst fpga_inst of fpga is
newattr libName = "xilinx_devices";
partnumber = "122-1717-ND";
newattr supplier = "DIGI-KEY";
newattr cost = "21.95";
// Signal pins from FPGA design.
clk = clk;
rst = rst;
rxd = rxd;
rxd_a = rxd_a;
txd = txd;
txd_a = txd_a;
sclk = sclk;
sdata = sdata;
sync = sync;
data = data;
.
.
.
end; 63

64. Motor Controller Board
• ~1200 lines of PHDL (25 pages of code)
• 30 device declarations
– 6 library files
• 672 nets
64

65. Motor Controller Board
Bill of Materials (CSV)
QUANTITY NAME REFDES PKG_TYPE COST LIBNAME MFGR PARTNUMBER SUPPLIER
1 top_tq144 U1 tq144 21.95 xilinx_devices XILINX 122-1717-ND DIGI-KEY
27 C0603 C1; C2; C3; C0603MP C7;0.12C9; C10; C11; C12; C21; C22;445-1313-1-ND C37; C38; C39; C40; C41; C4
C4; C5; C6; C8; rc-master-smd TDK C23; C24; C36; DIGI-KEY
18 C0603 C13; C14; C15; C16; C17; C18; C19; C20; C25; C26; C27; C28; C44; C63; C64; DIGI-KEY C94
C0603MP 0.08 rc-master-smd TDK 445-1311-1-ND C65; C66;
11 CP_1206MP/T
C29; C30; C31; C32; C33; C34; C35; C85; C86; C87; C92
C1206MP/T 0.47 rc-master-smd AVX 478-1655-1-ND DIGI-KEY
1 dipswitch S1 DS-08 1.14 switch-dil E-Switch 450-1366-ND DIGI-KEY
27 R0603 R1; R2; R3; R0603MP R7;0.02R9; R10; R11; R12; R13; R14;P4.7KGCT-ND R26; R27; R28; R32; R65; R6
R4; R5; R6; R8; rc-master-smd Panasonic R15; R16; R25; DIGI-KEY
8 LD0603 LD7; LD6; LD5; LD4; LD3; LD2; LD1; LD0
0603MP 0.15 led OSRAM 475-2506-1-ND DIGI-KEY
9 R0603 R17; R18; R19; R20; R21; R22; R23; R24; R83 Panasonic P390GCT-ND
R0603MP 0.02 rc-master-smd DIGI-KEY
2 RAM256KX16U2; U3 TSOPII44 6.6 memory-issi ISSI 706-1035-ND DIGI-KEY
1 OSC_50MHZ X1 SM77H 2.63 crystal Abracon 535-9330-1-ND DIGI-KEY
2 TL1105T S2; S3 TL1105T 0.58 switch E-Switch EG1827-ND DIGI-KEY
3 HDR_1X6 J1; J2; J7 1X06/90 pinhead
65

66. The Group Construct
group "SWITCHES" is
inst fpga_switches of dipswitch is
a = <vcco>;
b = sw_res;
end;
inst(7:0) sw_pulldown of R0603 is
value = "4.7k";
partNumber = "P4.7KGCT-ND";
combine.a = sw_res;
each.b = gnd;
end;
inst(7:0) sw_lim of R0603 is
value = "4.7k";
partNumber = "P4.7KGCT-ND";
combine.a = sw_res;
combine.b = sw;
Group Initial
end; name Arrayed
end;
Layout
66

67. Why PHDL? (the longer version)
• Open format
– Any text tools can read and manipulate
– Design files do not get corrupted
– Easily shared, exchanged, emailed
– Design files forward/backward compatible
across tool revisions
67

68. Why PHDL?
• IDEs
– Templates and auto completion
– Color syntax highlighting
– Search, search-and-replace
– Scripting
• Example: Eclipse
68

69. Why PHDL?
• SCCS (source code control system)
– Shared repository for designs and part
libraries
– Design versions, change
tracking/documentation
– Diff, revert
• Collaboration
• Reusability
• Cross probing
69

70. Why PHDL?
• Hierarchy
• Focus on functionality rather than looks of
schematic
• Easy to mis-wire in graphics
– Rats nests
– Missed endpoints
– High pin count packages span multiple pages
– Dangling wires across schematic pages
• Non-electrical parts trivial to add
70

71. Why PHDL?
• Automation
– Higher level constructs
– Arrays, hierarchy
– Refdes handling
– DRC available to user due to open format
– Lint-like tools easily written
• Automatic generation of design files
– Example: device generation from UCF file for
FPGAs
71

72. What’s Next?
• PHDL 2.0
– Hierarchy support
– Pin directions and DRC
– IDE Eclipse plugin
• Instance template generator
• Syntax coloring
• Content assist
• Hierarchy browser
• Refactoring
– Additional tool flows
72