This document provides guidance on writing to and erasing flash memory from firmware on Silicon Labs C8051 microcontroller devices. It discusses flash organization, basic read, write and erase operations, and guidelines for flash programming. Example code is provided for various device families demonstrating functions for reading, writing and erasing flash in a way that is portable across devices.
4. AN201
1. Introduction
The Flash memory on all Silicon Labs MCU devices is readable and writable from application code. This capability
allows user software to store values to the Flash such as calibration constants or system parameters, and to
implement a boot loading feature in which user firmware can be updated in-system from a remote site.
The Flash that is not used by application code can be treated like an EEPROM, thus negating the need to connect
an external EEPROM to the device.
This document starts with the basics of accessing Flash from application code on any device, including device
specific details. Then, it discusses advanced routines that can be developed using the basic routines. Finally, it
describes precautions to take when writing to Flash.
Example code for the basic and advanced Flash access routines for all devices is included at the end of this
application note.
2. Key Points
It is strongly recommended that the VDD monitor be enabled during Flash write and erase operations to prevent
data corruption resulting from power irregularities or power-down conditions.
Disable interrupts before setting PSWE to '1' to prevent interrupt service routines, which may access variables
in xdata space, from generating MOVX writes which could corrupt Flash memory.
Be cautious when using the 'Large' and 'Compact' memory models, which target xdata and pdata spaces for
user variables, both of which generate MOVX write opcodes.
In the C8051F3xx, C8051F4xx, and C8051F5xx series devices, a Lock and Key sequence must be executed
before each Flash write or erase operation.
In the C8051F3xx, C8051F4xx, and C8051F5xx series devices, attempts to read, write, or erase code memory
locations located in RESERVED space will generate a device reset.
Attempts to read, write, or erase code memory locations in RESERVED space will be ignored by the hardware
on F0xx, F1xx, and F2xx devices.
The CPU is stalled during Flash write and erase operations, although peripherals (UART, ADC, timers, etc.)
remain active.
Interrupts which are posted during a Flash write or erase operation will be held pending until the completion of
the Flash operation, after which time they will be serviced in priority order.
The Flash page containing the lock byte or bytes cannot be erased from application code.
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3. Flash Essentials
The Flash in different device series has many similarities including page sizes, lock bits, and the instructions used
to read and write to Flash. The main differences are the amount of Flash available, how the VDD monitor is
enabled, and how SFR registers are modified to allow Flash writes and erases.
Although the CPU is stalled during Flash write and erase operations, peripherals (UART, ADC, timers, etc.) remain
active. Interrupts posted during a Flash write or erase operation are held until the Flash operation has completed,
after which they are serviced in priority order.
3.1. Flash Organization
The Flash memory on most devices is organized into a set of 512-byte pages. See the Flash chapter of the device
data sheet for specific information. As an example, Figure 1 shows the Flash organization for the C8051F30x
series.
PROGRAM
MEMORY
0x1FFF
Reserved
0x1E00 Lock Byte Decoding
Lock Byte 0x1DFF
0x1DFE Bit Description
0x1C00 7 if any of these are
6 '0', Flash is Write/
Erase locked
5 across the C2
Flash memory
organized in 512-byte 4 interface
pages 3
if any of these are
2 '0', Flash is Read
0x0200 1 locked across the
C2 interface
0x0000
0
Figure 1. Flash Memory Organization and Security for the C8051F30x Series
Some devices also have a separate scratchpad area of Flash. This scratchpad area is ideal for storing constants
and system parameters because of its smaller size.
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3.2. Device Specific Notes
Various MCUs have features that require consideration when accessing Flash. These considerations are described
below.
3.2.1. C8051F12x Code Banking
The C8051F12x family of devices have 128KB of Flash which is divided into 4 banks. Addresses in the range
0x00000 to 0x07FFF are mapped to first bank of Flash. Addresses in the range of 0x08000 to 0x0FFFF are
mapped to one of the other three banks based on the settings of the PSBANK register. Whenever accessing Flash
from the address range 0x08000 to 0x07FFF, precaution must be taken to select the correct bank using the
PSBANK register.
3.2.2. C8051F3xx, C8051F4xx, and C8051F5xx Flash Unlock Bytes
All C8051F3xx, C8051F4xx, and C8051F5xx devices' writes and erases to Flash are protected with a lock and key
function. The Flash Lock and Key Register (FLKEY) must be written with the correct key codes, in sequence,
before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the
codes must be written in order. If the key codes are written out of order, or the wrong codes are written, Flash
writes and erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a
Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each
write or erase; the key codes must be written again before a following Flash operation can be performed.
3.2.3. Flash Timing
This applies to:
C8051F0xx
C8051F2xx
C8051F34x
C8051F35x
C8051F36x
C8051F41x
Some of the device families require a Flash timing register, FLSCL, to be set to correctly access Flash. The register
value is based upon the SYSCLK speed. This register only needs to be set once. See the relevant data sheet for
device specific information regarding the FLSCL register.
3.2.4. C8051F4xx and C8051F5xx VDD Monitor Level
The 'F41x and 'F52x-53x devices have two settings for the VDD monitor threshold - low and high. When writing or
erasing Flash, the VDD monitor threshold should be set to the high setting. See the Reset Sources chapter in the
device's data sheet for detailed information on enabling the high threshold.
3.3. Flash Read, Write, and Erase Operations
There are three basic operations that can be performed on the Flash: read, write, and erase. The basic read and
write operations read or write one byte from Flash. The erase operation applies to a full page of Flash.
Flash read operations are accomplished by using the standard 8051 MOVC instruction (in the C language, MOVC
instructions are generated by using pointers of memory type 'code'). Flash write and erase operations on Silicon
Labs MCU devices are accomplished by using the MOVX instruction. The default target for MOVX write operations
is external memory (XRAM); however, devices can be configured such that MOVX write operations target Flash
memory instead. MOVX instructions are generated in C by using pointers of memory type xdata or pdata.
Flash erase operations occur on page boundaries. The erase operation sets all the bits in the Flash page to logic 1.
Flash write operations, which set bits to logic 0, occur on single byte boundaries. To successfully complete a write
to Flash, the target bytes must be erased to 0xFF because the write instruction can only clear bits in a byte.
MOVX write operations on all Silicon Labs MCU devices can target Flash by setting bits in the
PSCTL register. When the PSWE bit (PSCTL.0) is set to a logic 1, MOVX write opcodes target Flash memory
instead of External Memory (XRAM). When both PSWE and PSEE (PSCTL.0 and PSCTL.1) are set to logic 1,
MOVX write opcodes erase the Flash page containing the target address. The target address can be any address
in the target page.
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4. Basic Flash Operations
The basic procedure to do the three basic Flash operations is the same on all devices. Some devices will require
setting additional registers to enable Flash operations. The pseudocode for the different operations is detailed
below for all devices. Also included below the pseudocode are the exceptions for the various device families. The
code that implements these routines for each device family is provided at the end of this application note in the files
named Fxxx_Primitives.h and Fxxx_Primitives.c.
4.1. Reading A Byte
1. Disable interrupts. This is optional for most devices, but recommended for the 'F12x and 'F13x devices.
2. Read the byte.
3. Restore interrupts if originally enabled.
Exceptions:
1. Set the SFLE bit before reading if the target address is in the scratchpad area.
2. If the device is the 'F12x or 'F13x, check the address and set the correct bank in the PSBANK register.
4.2. Writing A Byte
1. Disable interrupts. This is optional for most devices, but recommended for the 'F12x and 'F13x devices.
2. Set PSWE to '1' by writing PSCTL = 0x01 (PSEE must be '0').
3. Confirm VDD monitor is enabled.
4. Write the data to an erased byte.
5. Set PSWE and PSEE to '0' if no further erases are necessary.
6. Restore interrupts if originally enabled.
Exceptions:
1. Set the SFLE bit before writing if the target address is in the scratchpad are
2. If the device is a 'F3xx, 'F4xx, or 'F5xx device, write FLKEY = 0xA5 then FLKEY = 0xF1 before writing the byte.
3. If the device is the 'F12x or 'F13x, check the address and set the correct bank in the PSBANK register before writing the
byte.
4. For all ‘F0xx, ‘F1xx, and 'F2xx devices, enable Flash writes in the FLSCL Register (FLSCL = 0x01) before writing the byte.
Disable the bit after the byte has been written to Flash.
4.3. Erasing a Page
1. Disable interrupts. This is optional for most devices, but recommended for the 'F12x and 'F13x devices.
2. Set PSWE and PSEE to '1's by writing PSCTL = 0x03.
3. Confirm VDD monitor is enabled.
4. Write a data byte to any location within the 512-byte page to be erased.
5. Set PSWE and PSEE to '0' if no further erases are necessary.
6. Restore interrupts if originally enabled.
Exceptions:
1. Set the SFLE bit before writing if the target address is in the scratchpad area.
2. If the device is a ‘F3xx, 'F4xx, or 'F5xx device, write FLKEY = 0xA5 then FLKEY = 0xF1 before writing the byte.
3. If the device is the 'F12x or 'F13x, check the address and set the correct bank in the PSBANK register before writing the
byte.
4. For all ‘F0xx, ‘F1xx, and 'F2xx devices, enable Flash writes in the FLSCL Register (FLSCL = 0x01) before writing the byte.
Disable the bit after the byte has been written to Flash.
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4.4. Example Code Implementation Notes
The example code that comes with this application note is written for the largest Flash device in the device family.
The file name Fxxx_FlashPrimitives.h contains two #defines (FLASH_LAST and FLASH_TEMP) that must be
changed to reflect the target's actual Flash size.
Also, the example code explicitly enables the VDD monitor as a reset source through the RSTSRC register. The
code that writes to the RSTSRC register uses a direct assignment:
RSTSRC = 0x02;
This code will only enable the VDD monitor as a reset source, and will disable any other reset sources. If your
project requires other reset sources, change the example code to enable all of the required reset sources using a
single assignment to the RSTSRC register. This code is in the devices's Fxxx_FlashPrimitives.c file.
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5. Advanced Flash Operations
The basic routines described in Section 4 can be incorporated into more advanced routines that provide greater
flexibility. The following functions are commonly used Flash routines that expand upon the basic routines. The code
that implements these routines for each device family is provided at the end of this application note in the files
named Fxxx_Utils.h and Fxxx_Utils.c.
Flash_Read—This routine reads multiple bytes from Flash and returns a character string.
char * FLASH_Read (char *dest, FLADDR src, unsigned numbytes);
Flash_Write—This routine writes multiple bytes to Flash. This function assumes that the target bytes have been
cleared to 0xFF. If the bytes are not cleared to 0xFF, incorrect values might be stored in flash.
void FLASH_Write (FLADDR dest, char *src, unsigned numbytes);
Flash_Clear—This routines clears a string of bytes to 0xFF. The implementation of this function first copies the
data to temporary space, erases the page or pages, then copies the non-cleared bytes back to the original page or
pages. This routine requires a spare page of Flash to run, and it will clear up to one page size worth of data.
The FLASH_Clear routine can be used to clear bytes before they are written.
void FLASH_Clear (FLADDR addr, unsigned numbytes);
Flash_Update—This first clears the locations that are going to be written, and then writes the bytes. This routine
requires a spare page of Flash to run, and it will update up to one page size worth of data.
The FLASH_Update routine combines FLASH_Clear and FLASH_Write into one routine.
FLASH_Update (FLADDR dest, char *src, unsigned numbytes);
Flash_Copy—This routine copies bytes from one location in Flash to another location in Flash. It assumes that the
bytes are cleared to 0xFF. FLASH_Clear can be used to clear the bytes.
FLASH_Copy (FLADDR dest, FLADDR src, unsigned numbytes);
Flash_Fill—This routine fills bytes of Flash with a certain values. It assumes that bytes have been previously
cleared to 0xFF.
void FLASH_Fill (FLADDR addr, ULONG length, UCHAR fill);
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6. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk that the
write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of
VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alter-
ation of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the
device.
The following guidelines are recommended for any system which contains routines which write or erase Flash from
code.
6.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Ensure that the minimum VDD rise time specification of 1 ms is met. If the device has a minimum VDD
rise time specification, ensure that it is met. If the system cannot meet the rise time specification, then
add an external VDD brownout circuit to the RST pin of the device that holds the device in reset until
VDD reaches 2.7 V and re-asserts RST if VDD drops below 2.7 V.
3. Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code as pos-
sible. This should be the first set of instructions executed after the Reset Vector. For C-based systems,
this will involve modifying the startup code added by the C compiler. See your compiler documentation
for more details. Ensure that there are no delays in software between enabling the VDD monitor and
enabling the VDD monitor as a reset source.
4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a reset
source inside the functions that write and erase Flash memory. The VDD monitor enable instructions
should be placed just after the instruction to set PSWE to a '1', but before the Flash write or erase
operation instruction.
5. Ensure that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and
explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is
correct. "RSTSRC |= 0x02" is incorrect.
6. Ensure that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to check are
initialization code which enables other reset sources, such as the Missing Clock Detector or Compara-
tor, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can
quickly verify this.
7. If the device has a high and low threshold setting for the VDD monitor, enable the high setting.
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Table 1. VDD Monitor Enabling
Family How to enable the VDD monitor How to enable as a reset source
‘F00x (always enabled) (always enabled)
‘F01x (always enabled) (always enabled)
‘F02x Connect MONEN pin to VDD Enabled if MONEN pulled high
‘F04x Connect MONEN pin to VDD RSTSRC = 0x02;
‘F06x Connect MONEN pin to VDD RSTSRC = 0x02;
‘F12x, ‘F13x Connect MONEN pin to VDD RSTSRC = 0x02;
‘F2xx (always enabled on 48 pin package) Enabled if MONEN pulled high
Connect MONEN pin to VDD on 32 pin package
‘F30x (always enabled) RSTSRC = 0x02;1
‘F31x VDMEN = ‘1’; RSTSRC = 0x02;2
‘F32x VDMEN = ‘1’; RSTSRC = 0x02;2
‘F326 VDMEN = ‘1’; RSTSRC = 0x02;2
‘F33x VDMEN = ‘1’; RSTSRC = 0x02;2
‘F34x VDMEN = ‘1’; RSTSRC = 0x02;2
‘F35x VDMEN = ‘1’; RSTSRC = 0x02;2
‘F36x VDMEN = ‘1’; RSTSRC = 0x02;2
‘F41x VDMEN = '1'; VDMLVL = '1'; RSTSRC = 0x02;2
‘F52x, ‘F53x VDDMON = '1'; VDMLVL = '1'; RSTSRC = 0x02;2
Notes:
1. On the ‘F30x devices, enabling the VDD monitor by setting the PORSF bit when the VDD monitor is disabled may
cause a system reset.
2. In software which writes or erases Flash memory, the VDD monitor should be enabled as a reset source immediately
following setting VDMEN to a '1'.
6.2. PSWE Maintenance
8. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should
be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that
sets PSWE and PSEE both to a '1' to erase Flash pages.
9. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address updates
and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area.
10. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
11. Ensure that the Flash write and erase pointer variables are not located in XRAM. See your compiler
documentation for instructions regarding how to explicitly locate variables in different memory areas.
12. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
called with an illegal address does not result in modification of the Flash.
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6.3. System Clock
13. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
14. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
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7. Example Code
The following code examples are organized by device family because devices in the same family are code
compatible. These code examples target the device that has the largest Flash size in each family. The code
changes that need to be made for devices with a different Flash size are the locations of the temporary page and
last page of Flash. These addresses are located in FlashPrimitives.h. See the Flash section of the device's data
sheet for more information.
7.1. ‘F000
7.1.1. F000_FlashPrimitives.c
//-----------------------------------------------------------------------------
// F000_FlashPrimitives.c
//-----------------------------------------------------------------------------
// Copyright 2004 Silicon Laboratories, Inc.
//
// This program contains several useful utilities for writing and updating
// FLASH memory.
//
// AUTH: BW & GP
// DATE: 21 JUL 04
//
// Target: C8051F0xx
// Tool chain: KEIL C51 7.06
//
// Release 1.0
//
//-----------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------
#include "F000_FlashPrimitives.h"
#include <c8051F000.h>
//-----------------------------------------------------------------------------
// Structures, Unions, Enumerations, and Type Definitions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Global Constants
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Function Prototypes
//-----------------------------------------------------------------------------
// FLASH read/write/erase routines
void FLASH_ByteWrite (FLADDR addr, char byte);
unsigned char FLASH_ByteRead (FLADDR addr);
void FLASH_PageErase (FLADDR addr);
//-----------------------------------------------------------------------------
// Global Variables
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// FLASH Routines
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// FLASH_ByteWrite
//-----------------------------------------------------------------------------
//
// This routine writes <byte> to the linear FLASH address <addr>.
// Linear map is decoded as follows:
// Linear Address Device Address
// ------------------------------------------------
// 0x00000 - 0x0FFFF 0x0000 - 0xFFFF
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