Description: An arithmetic unit based on IEEE754 single precision standard for floating point numbers has been targeted to implement on Spartan-6 XC6SLX45 FPGA Board. The hardware description language used to program the FPGA chip was VHDL (very high speed integrated circuit hardware description language). The arithmetic unit implemented has a 32- bit processing unit which allowed limited arithmetic operations such as addition, Subtraction, multiplication and division. The overall coding style used was behavioural modelling synthesis and simulations were done and observed in Xilinx 14.7 and modelsim SE 6.4 version respectively. The final outcome of project revealed that proposed arithmetic unit was able to handle maximum frequency of 126.004 MHz (i.e. Minimum period of 7.936ns).

1. Department of Electronics and
Telecommunication Engineering
A Seminar on
“Floating point arithmetic unit
Implemented on FPGA using VHDL”
Guided by
Prof. H. M. Raza

2. Brief outline:
IEEE 754 format
Floating point unit
VHDL
FPGA
EDA Tools and softwares
Design of arithmetic units
Conclusion

3. Introduction to Floating Point IEEE 754
Standard
 Established in 1985 by IEEE
It has mainly two format
• Single Precision (32-bit)
• Double Precision(64-bit)

4. IEEE 754 single precision format
𝑁 = (−1) 𝑆
1.M*2 𝐸−127
Mantissa (M)Mantissa (M)

5. Conversion Examples
Consider 9.5 is to be converted in standard IEEE754 format.
9.5 can be represented in binary as 1001.10
After normalization 1.00110*23
Biasing is to be done to exponent 1.00110*23+127
Similarly -12.076 can be represented as:
9.5 = 0 10000010 00110000000000000000000
-12.076 = 1 10000010 10000010011011101110101

6. Conversion of IEEE754 to decimal
1 1011 0110 01100000000000000000000
−𝟏 𝟏
× 𝟐 𝟏𝟎𝟏𝟏𝟎𝟏𝟏𝟎−𝟎𝟏𝟏𝟏𝟏𝟏𝟏𝟏
× 𝟏. 𝟎𝟏𝟏
= −𝟏. 𝟑𝟕𝟓 × 𝟐 𝟓𝟓
= −49539595901075456.0
= −4.9539595901075456 ×𝟏𝟎 𝟏𝟔

7. What is ALU?
It is Arithmetic and logical unit
In simple words any unit which performs the
required mathematical computations

8. Limitations of basic ALU
It operates only on Integer values, hence less
precision.
When forced to be operated on floating
point numbers then it results in slow
operations and lags in accuracy

9. Floating point arithmetic unit
 FPAU is a arithmetic unit which is capable to
compute the floating point numbers (real
numbers)
 Floating-point operations are often pipelined,
which increases the speed of operation.

10. What is FPGA?
• It is a semiconductor device that can be
programmed after manufacturing.
• The FPGA-architecture consists of many logic
modules, which are placed in an array-
structure

11. FPGA architecture

12. Significant characteristics for the FPGA-
architecture
 Array of logic-modules
Different logic-modules possible
Routing-channels physically exits between
logic-modules
Every logic-module can be interconnected to
any other logic-modul or I/O-module

13. Overview of VHDL
 VHDL stands for Very High Speed Integrated
Circuit Hardware Description Language
VHDL is widely used to model digital systems
VHDL was originated in early 1980’s and was
standardized in 1987 by the IEEE

14. VHDL features
 Structural Specification
 Support for Design Hierarchy
 Library Support
 Support for Concurrent and Sequential Statements
 Type Declaration
 Use of subprograms

15. Design flow
The design file is written in VHDL language with the
extension .vhd and often named as its ENTITY’s name.
The major steps in design flow are:
 Compilation
 Optimization
 Place-and-route

16. VHDL Constructs
 Entity definition
 Architecture definition
 Configuration
 Process
 Subprogram
 Package
A VHDL design can be broken into multiple files. Each file contains
entity and architecture definitions, or packages.

17. VHDL Code Structure
Entity Declaration
Defines input/output ports
Architecture Declaration
Defines what the component does Variables,
Signals, Constants defines
Component Mapping
Interconnects previously defined
components/entities.

18. Different modeling schemes in VHDL
Behavioral
defines outputs as function of input Algorithms
but no implementation
Structural
Implements behavior by connecting components
with known behavior

19. Example
entity andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end andgate;
architecture Behavioral of andgate is
Begin
c <= a AND b;
end Behavioral;

20. EDA tools and softwares used
 Xilinx ISE design suit 14.7
This software is used to synthesize and simulate the VHDL code
developed.
 Target device: Atlys Spartan-6 Academic Development Kit
Spartan-6 XC6SLX45 FPGA
6,822 Spartan-6 logic slices , 43,661 Spartan-6 logic cells
Integrated Memory Controller Block (MCB)
2,088 Kbits of block RAM

21. Design and implementation of FPAU
In top-down design approach FPAU is designed
for four arithmetic modules, addition,
subtraction, multiplication and division.
Selection of any of the above functions in done
with the operation code (Op)

22. Block diagram of FPAU

23. Input output information
A,B : input operands
Op : input operation code
Clk : input clock
R : Output Result
Function of Operation Code(Op)
Op(1) Op(0) Operation
0 0 Addition
0 1 Subtraction
1 0 Multiplication
1 1 Division

24. Algorithm for
addition/subtraction
Step 1: Take difference of two exponents.
Take the larger exponent as the tentative
exponent of the result.
Step 2: Shift the Mantissa of the number
with the smaller exponent, right through a
number of bit positions that is equal to the
difference of exponents.
Step 3: Add/subtract the two Mantissas as
per sign bits and instruction and take the
result of two as the tentative mantissa of
result.
Step 4: Normalization of exponent and
mantissa

26. Algorithm for
Multiplication
Step 1: Add two exponents. Take the
result tentative exponent of the result.
Step 2: Multiply two mantissas
Step 3: Normalization
Step 4: set the sign bit

27. Block diagram of multiplier/divider

28. RESULTS
Inferred 1 Multiplier(s).
Inferred 31 Adder/Subtractor(s).
Inferred 256 D-type flip-flop(s).
Inferred 2 Comparator(s).
Inferred 141 Multiplexer(s).
 Timing Summary
Minimum period: 7.936ns (Maximum Frequency: 126.004MHz)
Synthesis summary

29. Simulation results while performing addition

30. Simulation results while performing multiplication

31. Conclusion
Synthesis of the Floating Point Unit targeted for
the FPGA device had been done using Xilinx-ISE
design suit 14.7. Synthesis result revels approximate
05% resource utilization i.e. 404 slices (202 CLB’s).
Correspondingly the logic verification of FPU is done
using ModelSim DE edition.