SlideShare ist ein Scribd-Unternehmen logo

1.prallelism

•Als PPT, PDF herunterladen•
•
Mahesh Kumar Attri
Mahesh Kumar Attri
1 von 30
Unit-4 Parallelism Chapter - 9
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Exploitation of Concurrency: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Instruction Pipeline (sec-9.4) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Four segment CPU Pipeline Fetch Instruction Decode & calculate effective Address Branch? Fetch Operand Execute Instruction Interrupt? Interrupt handling Update PC Empty Pipe Yes No No Yes
Timing of Instruction Pipeline Instruction Step 1 2 3 4 5 6 7 8 9 10 11 12 13 1 FI DA FO EX 2 FI DA FO 3 FI DA 4 FI - - FI DA FO EX 5 - - - FI DA FO EX 6 FI DA FO EX 7 FI DA FO EX
Pipeline Conflicts ,[object Object],[object Object],[object Object]
Instruction-level parallelism (ILP) ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The superscalar technique is associated with several identifying characteristics (within a given CPU core): ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor Level Parallelism ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object]
Amdahl's law ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
 
Basic Page Replacement ,[object Object],[object Object],[object Object],[object Object]
Page Replacement : OPT (Optimal Policy) ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
CAO Model Question Paper Unit – 3 ,[object Object],[object Object],[object Object],[object Object]
Modes of transfer (11.4) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Programmed I/O ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Interrupt Initiated IO ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Types of Interrupt ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object]
DMA (Direct Memory Access – 11.6 ) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],BR DBUS ABUS CPU RD BG WR
[object Object],Address Bus buffers Address registers Word count Register Control Register DS RS DMA RD Control logic WR BR BG Interrupt DMA Req DMA ACK To IO Device Data Bus buffers Data bus Address bus
CAO Model Question Paper Unit – 4 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Empfohlen

Register transfer and micro-operation
Register transfer and micro-operationRegister transfer and micro-operation
Register transfer and micro-operationNikhil Pandit
 
Input output interface
Input output interfaceInput output interface
Input output interfaceChrist University
 
Semophores and it's types
Semophores and it's typesSemophores and it's types
Semophores and it's typesNishant Joshi
 
Bus and memory transfer
Bus and memory transferBus and memory transfer
Bus and memory transferAnil Pokhrel
 
Micro Programmed Control Unit
Micro Programmed Control UnitMicro Programmed Control Unit
Micro Programmed Control UnitKamal Acharya
 
Superscalar & superpipeline processor
Superscalar & superpipeline processorSuperscalar & superpipeline processor
Superscalar & superpipeline processorMuhammad Ishaq
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memoryMazin Alwaaly
 
Parallel processing
Parallel processingParallel processing
Parallel processingrajshreemuthiah
 

Empfohlen

Register transfer and micro-operation
Register transfer and micro-operationRegister transfer and micro-operation
Register transfer and micro-operationNikhil Pandit
 
Input output interface
Input output interfaceInput output interface
Input output interfaceChrist University
 
Semophores and it's types
Semophores and it's typesSemophores and it's types
Semophores and it's typesNishant Joshi
 
Bus and memory transfer
Bus and memory transferBus and memory transfer
Bus and memory transferAnil Pokhrel
 
Micro Programmed Control Unit
Micro Programmed Control UnitMicro Programmed Control Unit
Micro Programmed Control UnitKamal Acharya
 
Superscalar & superpipeline processor
Superscalar & superpipeline processorSuperscalar & superpipeline processor
Superscalar & superpipeline processorMuhammad Ishaq
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memoryMazin Alwaaly
 
Parallel processing
Parallel processingParallel processing
Parallel processingrajshreemuthiah
 
Parallelism
ParallelismParallelism
ParallelismMd Raseduzzaman
 
Register transfer language
Register transfer languageRegister transfer language
Register transfer languageSanjeev Patel
 
Chapter 8
Chapter 8Chapter 8
Chapter 8Er. Nawaraj Bhandari
 
Computer architecture pipelining
Computer architecture pipeliningComputer architecture pipelining
Computer architecture pipeliningMazin Alwaaly
 
Turing machine by_deep
Turing machine by_deepTuring machine by_deep
Turing machine by_deepDeepjyoti Kalita
 
Synchronous counters
Synchronous countersSynchronous counters
Synchronous countersLee Diaz
 
top level view of computer function and interconnection
top level view of computer function and interconnectiontop level view of computer function and interconnection
top level view of computer function and interconnectionSajid Marwat
 
Compiler design
Compiler designCompiler design
Compiler designThakur Ganeshsingh Thakur
 
Multiprocessor system
Multiprocessor system Multiprocessor system
Multiprocessor system Mr. Vikram Singh Slathia
 
Memory organization
Memory organizationMemory organization
Memory organizationishapadhy
 
Load Balancing In Distributed Computing
Load Balancing In Distributed ComputingLoad Balancing In Distributed Computing
Load Balancing In Distributed ComputingRicha Singh
 
Microprogram Control
Microprogram Control Microprogram Control
Microprogram Control Anuj Modi
 
Compiler unit 2&3
Compiler unit 2&3Compiler unit 2&3
Compiler unit 2&3BBDITM LUCKNOW
 
Pumping lemma Theory Of Automata
Pumping lemma Theory Of AutomataPumping lemma Theory Of Automata
Pumping lemma Theory Of Automatahafizhamza0322
 
Unit 4 memory system
Unit 4 memory systemUnit 4 memory system
Unit 4 memory systemchidabdu
 
Amdahl`s law -Processor performance
Amdahl`s law -Processor performanceAmdahl`s law -Processor performance
Amdahl`s law -Processor performanceCOMSATS Institute of Information Technology
 
Memory Organization
Memory OrganizationMemory Organization
Memory OrganizationKamal Acharya
 
Propositional And First-Order Logic
Propositional And First-Order LogicPropositional And First-Order Logic
Propositional And First-Order Logicankush_kumar
 
Pipelining and ILP (Instruction Level Parallelism)
Pipelining and ILP (Instruction Level Parallelism) Pipelining and ILP (Instruction Level Parallelism)
Pipelining and ILP (Instruction Level Parallelism) A B Shinde
 
Memory mapped I/O and Isolated I/O
Memory mapped I/O and Isolated I/OMemory mapped I/O and Isolated I/O
Memory mapped I/O and Isolated I/OBharat Kharbanda
 
1.prallelism
1.prallelism1.prallelism
1.prallelismMahesh Kumar Attri
 
Mac
MacMac
MacMahesh Kumar Attri
 

Weitere ähnliche Inhalte

Was ist angesagt?

Register transfer language
Register transfer languageRegister transfer language
Register transfer languageSanjeev Patel
 
Computer architecture pipelining
Computer architecture pipeliningComputer architecture pipelining
Computer architecture pipeliningMazin Alwaaly
 
Synchronous counters
Synchronous countersSynchronous counters
Synchronous countersLee Diaz
 
top level view of computer function and interconnection
top level view of computer function and interconnectiontop level view of computer function and interconnection
top level view of computer function and interconnectionSajid Marwat
 
Memory organization
Memory organizationMemory organization
Memory organizationishapadhy
 
Load Balancing In Distributed Computing
Load Balancing In Distributed ComputingLoad Balancing In Distributed Computing
Load Balancing In Distributed ComputingRicha Singh
 
Microprogram Control
Microprogram Control Microprogram Control
Microprogram Control Anuj Modi
 
Pumping lemma Theory Of Automata
Pumping lemma Theory Of AutomataPumping lemma Theory Of Automata
Pumping lemma Theory Of Automatahafizhamza0322
 
Unit 4 memory system
Unit 4 memory systemUnit 4 memory system
Unit 4 memory systemchidabdu
 
Propositional And First-Order Logic
Propositional And First-Order LogicPropositional And First-Order Logic
Propositional And First-Order Logicankush_kumar
 
Pipelining and ILP (Instruction Level Parallelism)
Pipelining and ILP (Instruction Level Parallelism) Pipelining and ILP (Instruction Level Parallelism)
Pipelining and ILP (Instruction Level Parallelism) A B Shinde
 
Memory mapped I/O and Isolated I/O
Memory mapped I/O and Isolated I/OMemory mapped I/O and Isolated I/O
Memory mapped I/O and Isolated I/OBharat Kharbanda
 

Was ist angesagt? (20)

Parallelism
ParallelismParallelism
Parallelism
 
Register transfer language
Register transfer languageRegister transfer language
Register transfer language
 
Chapter 8
Chapter 8Chapter 8
Chapter 8
 
Computer architecture pipelining
Computer architecture pipeliningComputer architecture pipelining
Computer architecture pipelining
 
Turing machine by_deep
Turing machine by_deepTuring machine by_deep
Turing machine by_deep
 
Synchronous counters
Synchronous countersSynchronous counters
Synchronous counters
 
top level view of computer function and interconnection
top level view of computer function and interconnectiontop level view of computer function and interconnection
top level view of computer function and interconnection
 
Compiler design
Compiler designCompiler design
Compiler design
 
Multiprocessor system
Multiprocessor system Multiprocessor system
Multiprocessor system
 
Memory organization
Memory organizationMemory organization
Memory organization
 
Load Balancing In Distributed Computing
Load Balancing In Distributed ComputingLoad Balancing In Distributed Computing
Load Balancing In Distributed Computing
 
Microprogram Control
Microprogram Control Microprogram Control
Microprogram Control
 
Compiler unit 2&3
Compiler unit 2&3Compiler unit 2&3
Compiler unit 2&3
 
Pumping lemma Theory Of Automata
Pumping lemma Theory Of AutomataPumping lemma Theory Of Automata
Pumping lemma Theory Of Automata
 
Unit 4 memory system
Unit 4 memory systemUnit 4 memory system
Unit 4 memory system
 
Amdahl`s law -Processor performance
Amdahl`s law -Processor performanceAmdahl`s law -Processor performance
Amdahl`s law -Processor performance
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
 
Propositional And First-Order Logic
Propositional And First-Order LogicPropositional And First-Order Logic
Propositional And First-Order Logic
 
Pipelining and ILP (Instruction Level Parallelism)
Pipelining and ILP (Instruction Level Parallelism) Pipelining and ILP (Instruction Level Parallelism)
Pipelining and ILP (Instruction Level Parallelism)
 
Memory mapped I/O and Isolated I/O
Memory mapped I/O and Isolated I/OMemory mapped I/O and Isolated I/O
Memory mapped I/O and Isolated I/O
 

Andere mochten auch

SPARC T1 MMU Architecture
SPARC T1 MMU ArchitectureSPARC T1 MMU Architecture
SPARC T1 MMU ArchitectureKaushik Patra
 
Finite automata intro
Finite automata introFinite automata intro
Finite automata introlavishka_anuj
 
Partnership revision questions ay 2014 2015
Partnership revision questions ay 2014 2015Partnership revision questions ay 2014 2015
Partnership revision questions ay 2014 2015JUMA BANANUKA
 
Computer architecture kai hwang
Computer architecture kai hwangComputer architecture kai hwang
Computer architecture kai hwangSumedha
 
Accounting for Partnerships
Accounting for PartnershipsAccounting for Partnerships
Accounting for PartnershipsArthik Davianti
 
Lecture 3
Lecture 3Lecture 3
Lecture 3Mr SMAK
 
INSTRUCTION LEVEL PARALLALISM
INSTRUCTION LEVEL PARALLALISMINSTRUCTION LEVEL PARALLALISM
INSTRUCTION LEVEL PARALLALISMKamran Ashraf
 
Instruction Level Parallelism (ILP) Limitations
Instruction Level Parallelism (ILP) LimitationsInstruction Level Parallelism (ILP) Limitations
Instruction Level Parallelism (ILP) LimitationsJose Pinilla
 
Parallelism
ParallelismParallelism
ParallelismMs. Ross
 
Accounting for Partnership by Guerrero et al
Accounting for Partnership by Guerrero et alAccounting for Partnership by Guerrero et al
Accounting for Partnership by Guerrero et alAdrian Chris Arevalo
 
Partnership accounting
Partnership accountingPartnership accounting
Partnership accountingKhuram Shahzad
 

Andere mochten auch (20)

1.prallelism
1.prallelism1.prallelism
1.prallelism
 
Mac
MacMac
Mac
 
shashank_micro92_00697015
shashank_micro92_00697015shashank_micro92_00697015
shashank_micro92_00697015
 
SPARC T1 MMU Architecture
SPARC T1 MMU ArchitectureSPARC T1 MMU Architecture
SPARC T1 MMU Architecture
 
Finite automata intro
Finite automata introFinite automata intro
Finite automata intro
 
Vliw
VliwVliw
Vliw
 
Hyper threading
Hyper threadingHyper threading
Hyper threading
 
Partnership revision questions ay 2014 2015
Partnership revision questions ay 2014 2015Partnership revision questions ay 2014 2015
Partnership revision questions ay 2014 2015
 
Computer architecture kai hwang
Computer architecture kai hwangComputer architecture kai hwang
Computer architecture kai hwang
 
Accounting for Partnerships
Accounting for PartnershipsAccounting for Partnerships
Accounting for Partnerships
 
Lecture 3
Lecture 3Lecture 3
Lecture 3
 
INSTRUCTION LEVEL PARALLALISM
INSTRUCTION LEVEL PARALLALISMINSTRUCTION LEVEL PARALLALISM
INSTRUCTION LEVEL PARALLALISM
 
Instruction Level Parallelism (ILP) Limitations
Instruction Level Parallelism (ILP) LimitationsInstruction Level Parallelism (ILP) Limitations
Instruction Level Parallelism (ILP) Limitations
 
Parallelism
ParallelismParallelism
Parallelism
 
07 Input Output
07 Input Output07 Input Output
07 Input Output
 
Accounting for Partnership by Guerrero et al
Accounting for Partnership by Guerrero et alAccounting for Partnership by Guerrero et al
Accounting for Partnership by Guerrero et al
 
Partnership accounts
Partnership accountsPartnership accounts
Partnership accounts
 
Computer System Organization
Computer System OrganizationComputer System Organization
Computer System Organization
 
Partnership accounting
Partnership accountingPartnership accounting
Partnership accounting
 
Types of parallelism
Types of parallelismTypes of parallelism
Types of parallelism
 

Ähnlich wie 1.prallelism

Hardback solution to accelerate multimedia computation through mgp in cmp
Hardback solution to accelerate multimedia computation through mgp in cmpHardback solution to accelerate multimedia computation through mgp in cmp
Hardback solution to accelerate multimedia computation through mgp in cmpeSAT Publishing House
 
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docx
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxCS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docx
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxfaithxdunce63732
 
Measuring Performance by Irfanullah
Measuring Performance by IrfanullahMeasuring Performance by Irfanullah
Measuring Performance by Irfanullahguest2e9811e
 
Tdt4260 miniproject report_group_3
Tdt4260 miniproject report_group_3Tdt4260 miniproject report_group_3
Tdt4260 miniproject report_group_3Yulong Bai
 
What is simultaneous multithreading
What is simultaneous multithreadingWhat is simultaneous multithreading
What is simultaneous multithreadingFraboni Ec
 
Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP
Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP
Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP IJCSEIT Journal
 
Operating system - Process and its concepts
Operating system - Process and its conceptsOperating system - Process and its concepts
Operating system - Process and its conceptsKaran Thakkar
 
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTION
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTIONLEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTION
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTIONcscpconf
 
Learning scheduler parameters for adaptive preemption
Learning scheduler parameters for adaptive preemptionLearning scheduler parameters for adaptive preemption
Learning scheduler parameters for adaptive preemptioncsandit
 
The effective way of processor performance enhancement by proper branch handling
The effective way of processor performance enhancement by proper branch handlingThe effective way of processor performance enhancement by proper branch handling
The effective way of processor performance enhancement by proper branch handlingcsandit
 
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...cscpconf
 
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...IJCSEA Journal
 
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTING
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGDYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTING
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGcscpconf
 
Pipelining in Computer System Achitecture
Pipelining in Computer System AchitecturePipelining in Computer System Achitecture
Pipelining in Computer System AchitectureYashiUpadhyay3
 
Operating system Q/A
Operating system Q/AOperating system Q/A
Operating system Q/AAbdul Munam
 
Sheet1Address60741024Offsetaddress0102450506074120484026230723002p.docx
Sheet1Address60741024Offsetaddress0102450506074120484026230723002p.docxSheet1Address60741024Offsetaddress0102450506074120484026230723002p.docx
Sheet1Address60741024Offsetaddress0102450506074120484026230723002p.docxbagotjesusa
 

Ähnlich wie 1.prallelism (20)

Hardback solution to accelerate multimedia computation through mgp in cmp
Hardback solution to accelerate multimedia computation through mgp in cmpHardback solution to accelerate multimedia computation through mgp in cmp
Hardback solution to accelerate multimedia computation through mgp in cmp
 
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docx
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxCS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docx
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docx
 
Measuring Performance by Irfanullah
Measuring Performance by IrfanullahMeasuring Performance by Irfanullah
Measuring Performance by Irfanullah
 
Tdt4260 miniproject report_group_3
Tdt4260 miniproject report_group_3Tdt4260 miniproject report_group_3
Tdt4260 miniproject report_group_3
 
What is simultaneous multithreading
What is simultaneous multithreadingWhat is simultaneous multithreading
What is simultaneous multithreading
 
Parallel Processing.pptx
Parallel Processing.pptxParallel Processing.pptx
Parallel Processing.pptx
 
Computer architecture
Computer architectureComputer architecture
Computer architecture
 
Oversimplified CA
Oversimplified CAOversimplified CA
Oversimplified CA
 
Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP
Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP
Performance Analysis of Parallel Algorithms on Multi-core System using OpenMP
 
Operating system - Process and its concepts
Operating system - Process and its conceptsOperating system - Process and its concepts
Operating system - Process and its concepts
 
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTION
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTIONLEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTION
LEARNING SCHEDULER PARAMETERS FOR ADAPTIVE PREEMPTION
 
Learning scheduler parameters for adaptive preemption
Learning scheduler parameters for adaptive preemptionLearning scheduler parameters for adaptive preemption
Learning scheduler parameters for adaptive preemption
 
The effective way of processor performance enhancement by proper branch handling
The effective way of processor performance enhancement by proper branch handlingThe effective way of processor performance enhancement by proper branch handling
The effective way of processor performance enhancement by proper branch handling
 
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...
 
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...
 
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTING
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGDYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTING
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTING
 
Pipelining in Computer System Achitecture
Pipelining in Computer System AchitecturePipelining in Computer System Achitecture
Pipelining in Computer System Achitecture
 
Chap2 slides
Chap2 slidesChap2 slides
Chap2 slides
 
Operating system Q/A
Operating system Q/AOperating system Q/A
Operating system Q/A
 
Sheet1Address60741024Offsetaddress0102450506074120484026230723002p.docx
Sheet1Address60741024Offsetaddress0102450506074120484026230723002p.docxSheet1Address60741024Offsetaddress0102450506074120484026230723002p.docx
Sheet1Address60741024Offsetaddress0102450506074120484026230723002p.docx
 

Mehr von Mahesh Kumar Attri

Errror Detection and Correction
Errror Detection and CorrectionErrror Detection and Correction
Errror Detection and CorrectionMahesh Kumar Attri
 
Staffing & manpower planning(9)
Staffing & manpower planning(9)Staffing & manpower planning(9)
Staffing & manpower planning(9)Mahesh Kumar Attri
 

Mehr von Mahesh Kumar Attri (20)

Web technologies
Web technologiesWeb technologies
Web technologies
 
Plant layout
Plant layoutPlant layout
Plant layout
 
application layers
application layersapplication layers
application layers
 
Multiplexing
MultiplexingMultiplexing
Multiplexing
 
Ch08 1
Ch08 1Ch08 1
Ch08 1
 
Lect21 09-11
Lect21 09-11Lect21 09-11
Lect21 09-11
 
work measurement
work measurementwork measurement
work measurement
 
production management
production managementproduction management
production management
 
Fom (pm)
Fom (pm)Fom (pm)
Fom (pm)
 
Errror Detection and Correction
Errror Detection and CorrectionErrror Detection and Correction
Errror Detection and Correction
 
Data Communication
Data CommunicationData Communication
Data Communication
 
Lecture 5
Lecture 5Lecture 5
Lecture 5
 
International marketing
International marketingInternational marketing
International marketing
 
Ch01
Ch01Ch01
Ch01
 
OSI models
OSI modelsOSI models
OSI models
 
As department
As departmentAs department
As department
 
2.computer org.
2.computer org.2.computer org.
2.computer org.
 
Staffing & manpower planning(9)
Staffing & manpower planning(9)Staffing & manpower planning(9)
Staffing & manpower planning(9)
 
Science & art (2) 2
Science & art (2) 2Science & art (2) 2
Science & art (2) 2
 
Recruitment(10)
Recruitment(10)Recruitment(10)
Recruitment(10)
 

1.prallelism

  • 1. Unit-4 Parallelism Chapter - 9
  • 2.
  • 3.
  • 4.
  • 5.
  • 6. Four segment CPU Pipeline Fetch Instruction Decode & calculate effective Address Branch? Fetch Operand Execute Instruction Interrupt? Interrupt handling Update PC Empty Pipe Yes No No Yes
  • 7. Timing of Instruction Pipeline Instruction Step 1 2 3 4 5 6 7 8 9 10 11 12 13 1 FI DA FO EX 2 FI DA FO 3 FI DA 4 FI - - FI DA FO EX 5 - - - FI DA FO EX 6 FI DA FO EX 7 FI DA FO EX
  • 8.
  • 9.
  • 10.
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.  
  • 17.
  • 18.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23.
  • 24.
  • 25.
  • 26.
  • 27.
  • 28.
  • 29.
  • 30.