This document discusses high performance computing and topics related to cache coherence and vector processing. It provides an overview of cache coherence approaches including write-back and write-through implementations. It also describes hardware-based cache coherence solutions like directory and snoopy protocols. The directory protocol uses a centralized controller while snoopy protocol relies on broadcast messages. Specific cache coherence protocols like MESI and write-invalidate are explained. Vector processing and Amdahl's law on parallel programming speedup are also briefly mentioned.
4. Cache Coherence In SMP or NUMA, multiple copies of cache Each copy may have a different value of data item Maintain Coherency How?
5. Cache Coherence: Two Approaches Write back: Update Main memory once cache is flushed. Write through: Write is updated to cache as well as to the main memory.
6. Implementations Software Solutions: Compile time decision Conservative Inefficient cache utilization Hardware Solutions: Runtime decision More effective
8. Directory Centralized Controller Individual cache controller makes a request Centralized controller checks and issues command Updates information
9. Directory Write Processor requests exclusive writes Controller sends message Invalidates Read Issues command to the processor Holding Processor Writes back to MM Read permitted
16. Parallel programming and Amdahl's Law Suppose 1/N time for sequential code And 1-1/N for the parallel
17. Amdahl's Law Speedup: speed gain of using parallel processor vs. single processor Speed= 1/(s+(p/N)) S=sequential code, p = parallel code, N= no. of processors S= T(1)/ T(j) For j parallel processors As problem size increases, p may rise and s may decrease