Fill in the blanks for the Verilog HDL behavioral description for the Mealy FSM below. In the state diagram below, note that the notation on the transition is of the form in/out. For example, the transition from state S0 to S1 has 1/0, which corresponds to in=1 and out =0 (Answers are case sensitive) module seq_detectorl input x,clk,reset, output reg z ); parameter S0=0,S1=1,S2=2,S3=3; reg [1:0] PS,NS ; //sequential state register block always @ (posedge clk or posedge reset) if (reset) PS<=50; else PS<=NS; //sequential output block always @ (posedge clk or posedge reset) if (reset) z<=1b else z<=(PS==)&&x; //combinational state assignment block always @(x) begin case(PS) S0:NS=x?S1:50 S1:NS =x?:S2; S2:NS=x?53:50.

1. Fill in the blanks for the Verilog HDL behavioral description for the Mealy FSM below. In the
state diagram below, note that the notation on the transition is of the form in/out. For example,
the transition from state S0 to S1 has 1/0, which corresponds to in=1 and out =0 (Answers are
case sensitive) module seq_detectorl input x,clk,reset, output reg z ); parameter
S0=0,S1=1,S2=2,S3=3; reg [1:0] PS,NS ; //sequential state register block always @ (posedge clk
or posedge reset) if (reset) PS<=50; else PS<=NS; //sequential output block always @ (posedge
clk or posedge reset) if (reset) z<=1b else z<=(PS==)&&x; //combinational state assignment
block always @(x) begin case(PS) S0:NS=x?S1:50 S1:NS =x?:S2; S2:NS=x?53:50