Write the VHDL code for a 2-4 Decoder with an Enable input. You can refer to the VHDL_note.ppt for more help. Solution Library ieee; USE ieee.std_logic_1164.all; ENTITY decoder is PORT ( w : IN STD_LOGIC_ECTOR(1 DOWNTO 0); En : IN STD_LOGIC; y : OUT STD_LOGIC_ECTOR(1 DOWNTO 0); END decoder; ARCHITECTURE Behaviour OF decoder is BEGIN process (En , w) begin y <= x\"0\"; if(En == \'1\') then case(w) is when \"00\" => y <= 1000; when \"01\" => y <= 0100; when \"10\" => y <= 0010; when \"11\" => y <= 0001; when \"others\" => y <= 0000; end case; end if; end process; end Behaviour;.