Design a lag-lead compensator using the root locus method for the system shown in Figure 2 so that the system will operate at 20% overshoot and a two-fold or more reduction in settling time. Furthermore, the compensated system must exhibit a ten fold or more improvement in settling time R(s) E(s) C(s) Figure 1: Control Design Problem, Chapter 9 Solution Figure 2 is missing and the figure 1 cant be solved for the above requirements please upload the proper image or specify the function properly.

1. design a modified ring counter (b) Design a Johnson Counter, using D flip flops, to produce four
process control output wave trains from an input clock Show the basic counter that produces the
A, B, C and D outputs and draw the ABCD waveforms on the diagram below. Design the
minimized decoding circuits.
Solution
** Truth table:-
State Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
Four edge-triggered D flip-flops are connected to form a Johnson counter. Notice the Q output of
the flip-flop is connected to the D input of the first flip-flop. (b) The sequence table for the four-
bit Johnson counter.
At this point each flip-flop is set and has the value of 1, so when the next clock pulse is received
FF3 sends its Q (Q NOT) output (0) back to FF0 so that the four flip-flops show a value of 0111.
During the next steps, each flip-flop is reset to 0 in sequential order until the value of 0001
occurs. At this point the next time the shift register is pulsed, the count starts over again.
From this example, notice that the four-bit Johnson counter counts values 0-7. If a fifth flip-flop
is added, the Johnson counter could count values 0-9, and each additional flip-flop in the counter
allows the count to move up by a total of two.
In the sequence notice that the shift register is empty when the count begins and all flip-flops are
reset to provide the four-bit value of 0000. During the next step when the clock pulse is provided
at the D input, the first flip-flop will be set HI. The set of four flip-flops will now show the value
of 1000. When the next clock pulse is provided, flip-flop FF0 sends its value of 1 to FF1, so the
value of the four flip-flops is 1100.
During the next step when the clock pulse is received, the original two bits are shifted to FF2 and
the value of the four flip-flops is 1110. In the next step when the clock pulse is received, the bits
are all shifted to the right so the value of the four flip-flops is now 1111