8237 / 8257 DMA - DIRECT MEMORY ACCESS

1. AJAL.A.J
Assistant Professor –Dept of ECE,
UNIVERSAL ENGINEERING COLLEGE
Mob: 8907305642 MAIL: ec2reach@gmail.com

2. •The DMA I/O technique
provides direct access to
the memory while the
microprocessor is
temporarily disabled.

3. Three ways to synchronize the
processor to data rate of
peripherals:
1- Polling: which provides a fast response but it the
processor recourses are dedicated to one peripheral.
2- Interrupt approach: is much more efficient. the
processor only services the peripheral when data is
required. requires high software overhead.
3-DMA is a third solution but it increases the
complexity of the hardware system.

4. DMA
• Direct Memory Access.
• In memory-memory or memory-peripherals communication, the
processor is a “middleman” which is not really needed.
• Used with HOLD HOLDA signals.
• DMA requires another processor - The DMA Controller or DMACto generate the memory and I/O addresses.
• 8237 is a DMAC.
• In IBM PC, 8237 was used to speed up the read or write
operation by the slow 8088 processor.
• Nowadays, It is usually used by sound cards and by
memory controllers to generate row address for
refreshing.

5. I/O Data Transfer

6. Basic DMA concept
Direct memory access (DMA) is a feature of modern computer
systems that allows certain hardware subsystems to read/write data
to/from memory without microprocessor intervention, allowing the
processor to do other work.
Used in disk controllers, video/sound cards etc, or
between memory locations
.
Typically, the CPU initiates DMA transfer, does other operations while
the transfer is in progress, and receives an interrupt from the DMA
controller once the operation is complete.
Can create cache coherency problems (the data in the
cache may be different from the data in the external memory after
DMA)

7. B
ASIC DM T RM
A E INOL
OGY
DMA channel: system pathway used by a
device to transfer information directly to and
from memory. There are usually 8 in a
computer system
DMA controller: dedicated hardware used
for controlling the DMA operation
Single-cycle mode: DMA data transfer is
done one byte at a time
Burst-mode: DMA transfer is finished when
all data has been moved

8. DMA pins and timing
• x86 Interrupt Pins
– HOLD: DMA request.
• Sampled in the middle of any clocking cycle
– HLDA: DMA acknowledge signal.
• The address, data and control buses are set to high-Z,
so the I/O devices can control the system bus
8

9. •
•
•
DMA on the 8086
Microprocessor
The CPU may have to wait (hold cycles).
The DMA will then let the device that requested the DMA transfer know
that the transfer is commencing by asserting the -DACK signal.
Once the data has been transferred, The DMA will de-assert the -DACK2
signal, so that the FDC knows it must stop placing data on the bus.
• The DMA will now check to see if any of the other DMA
channels have any work to do. If none of the channels have
their DRQ lines asserted, the DMA controller has completed
its work and will now tri-state the -MEMR, -MEMW, -IOR,
-IOW and address signals.
•
Finally, the DMA will de-assert the HOLD signal. The CPU sees this, and
de-asserts the HOLDA signal. Now the CPU resumes control of the buses
and address lines, and it resumes executing instructions and accessing
main memory and the peripherals.
9

10. 8237 pins
• CLK: System clock
• CS΄: Chip select (decoder output)
8237
• RESET: Clears registers, sets mask register
• READY: 0 for inserting wait states
• HLDA: Signals that the μp has relinquished buses
• DREQ3 – DREQ0: DMA request input for each channel
• DB7-DB0: Data bus pins
• IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
• IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or as
output to signal the end of the DMA transfer
• A3-A0: Address pins for selecting internal registers
• A7-A4: Outputs that provide part of the DMA transfer address
• HRQ: DMA request output
• DACK3-DACK0: DMA acknowledge for each channel.
• AEN: Address enable signal
• ADSTB: Address strobe
• MEMR΄: Memory read output used in DMA read cycle
10
• MEMW΄: Memory write output used in DMA write cycle

11. 8237/
8257

12. Minimal System with a
DMA Controller
CPU
Interrupt
Bus
Arbiter
Memory
On-Chip-Bus
Request
DMA
Controller
Acknowledge
Peripheral
Device

13. 8237 DMA controller

14. Description of pin
diagram
 D0-D7:
 it is a bidirectional ,tri state ,Buffered
,Multiplexed data (D0-D7)and (A8-A15).
 In the slave mode it is a bidirectional (Data is
moving).
 In the Master mode it is a unidirectional
(Address is moving).

15. IOR:
 It is active low ,tristate ,buffered ,Bidirectional
lines.
 In the slave mode it function as a input line. IOR
signal is generated by microprocessor to read the
contents 8257 registers.
 In the master mode it function as a output line.
IOR signal is generated by 8257 during write cycle

16. IOW:
 It is active low ,tristate ,buffered ,Bidirectional
control lines.
 In the slave mode it function as a
input line. IOR signal is generated by
microprocessor to write the contents 8257
registers.
 In the master mode it function as a output line.
IOR signal is generated by 8257 during read cycle

17. CLK:
 It is the input line ,connected with TTL clock generator.
 This signal is ignored in slave mode.
RESET:
 Used to clear mode set registers and status registers
A0-A3:
These are the tristate, buffer, bidirectional address lines.
In slave mode ,these lines are used as address
inputs lines and internally decoded to access the internal
registers.
In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on the lines.

18. CS:
 It is active low, Chip select input line.
 In the slave mode, it is used to select the chip.
 In the master mode, it is ignored.
A4-A7:
These are the tristate, buffer, output address lines.
In slave mode ,these lines are used as address
input lines.
In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on
the lines.

19. READY:
 It is a asynchronous input line.
 In master mode,
When ready is high it receives the signal.
When ready is low, it adds wait state between S1
and S3
 In slave mode ,
this signal is ignored.
HRQ:
 It is used to receiving the hold request signal from
the output device.

20. HLDA:
 It is acknowledgment signal from microprocessor.
MEMR:
 It is active low ,tristate ,Buffered control output line.
 In slave mode, it is tristated.
 In master mode ,it activated during DMA read cycle.
MEMW:
 It is active low ,tristate ,Buffered control input line.
 In slave mode, it is tristated.
 In master mode ,it activated during DMA write cycle.

21. AEN (Address enable):




It is a control output line.
In master mode ,it is high
In slave mode ,it is low
Used it isolate the system address ,data ,and
control lines.
ADSTB: (Address Strobe)




It is a control output line.
Used to split data and address line.
It is working in master mode only.
In slave mode it is ignore.

22. TC (Terminal Count):
 It is a status of output line.
 It is activated in master mode only.
 It is high ,it selected the peripheral.
 It is low ,it free and looking for a new peripheral.
MARK:
 It is a modulo 128 MARK output line.
 It is activated in master mode only.
 It goes high ,after transferring every 128 bytes of
data block.

23. DRQ0-DRQ3 (DMA Request):
 These are the asynchronous peripheral request
input signal.
 The request signals is generated by external
peripheral device.
DACK0-DACK3:
 These are the active low DMA acknowledge
output lines.
 Low level indicate that ,peripheral is selected for
giving the information (DMA cycle).
 In master mode it is used for chip select.

24.  HLDA becomes active to indicate the processor
has placed its buses at high-impedance state.
 as can be seen in the timing diagram, there are
a few clock cycles between the time that HOLD
changes and until HLDA changes
 HLDA output is a signal to the requesting device
that the processor has relinquished control of its
memory and I/O space.
 one could call HOLD input a DMA request
input and HLDA output a DMA grant signal

25. 8237 block diagram
25

26. Description
 It containing Five main Blocks.
1. Data bus buffer
2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.

27. DATA BUS BUFFER:
 It contain tristate ,8 bit bi-directional buffer.
 Slave mode ,it transfer data between
microprocessor and internal data bus.
 Master mode ,the outputs A8-A15 bits of
memory address on data lines
(Unidirectional).
READ/CONTROL LOGIC:
 It control all internal Read/Write operation.
 Slave mode ,it accepts address bits and control
signal from microprocessor.
 Master mode ,it generate address bits and control
signal.

28. Control logic block:
It contains ,
1. Control logic
2. Mode set register and
3. Status Register.

CONTROL LOGIC:





Master mode ,It control the sequence of DMA
operation during all DMA cycles.
It generates address and control signals.
It increments 16 bit address and decrement 14 bit
counter registers.
It activate a HRQ signal on DMA channel Request.
Slave ,mode it is disabled.

29. FIGURE A DMA controller allows the peripheral to
interface directly with memory without processor
intervention. This allows the data transfer rate to approach
the access time of memory.
Types:
Sequential DMA
Simultaneous DMA

30. FIGURE Three methods (MODES) of DMA
operation: (a) byte; (b) burst; (c) block.

31. DMA is implemented using a
DMA controller
– DMA controller
• Acts as slave to processor
• Receives instructions from processor
• Example: Reading from an I/O device
– Processor gives details to the DMA controller
» I/O device number
» Main memory buffer address
» Number of bytes to transfer
» Direction of transfer (memory → I/O device, or
vice versa)

32. Steps in a DMA operation
 Processor initiates the DMA controller
 Gives device number, memory buffer pointer, …
 Called channel
initialization
 Once initialized, it is ready for data transfer

When ready, I/O device informs the DMA
controller
 DMA controller starts the data transfer process





Obtains bus by going through bus arbitration
Places memory address and appropriate control signals
Completes transfer and releases the bus
Updates memory address and count value
If more to read, loops back to repeat the process
 Notify the processor when done
 Typically uses an interrupt

33. DMA controller details

34. Modes of Operation
 Rotating priority Mode:
 The priority of the channels has a circular
sequence.
 Fixed Priority Rotating Mode:




The priority is fixed.
TC Stop Mode
Auto Load mode
Extended Write mode

35. DMA Cycles
1. DMA read
2. DMA write
3. DMA Verify