Different testing techniques used in VLSI to test the circuit are explained here.

1. VLSI TESTING TECHNIQUES
Mr. A. B. Shinde
Assistant Professor,
Electronics Engineering,
P.V.P.I.T., Budhgaon

2. BOOK: TESTING
2

3. NEED OF TESTING CIRCUIT
 There are several reasons for testing a logic circuit.
 When the circuit is first developed, it is necessary to verify that
the designed circuit meets the required functional and timing
specifications.
 When multiple copies are manufactured, it is essential to test
each copy to ensure that the manufacturing process has not
introduced any flaws.
 The basis of all testing techniques is to apply predefined sets of
inputs, called tests, to a circuit and compare the outputs observed
with the patterns that a correctly functioning circuit is supposed to
produce.
 The challenge is to derive a relatively small number of tests that
provide an adequate indication that the circuit is correct.
3

4. TESTING TECHNIQUES
 Types of Testing Circuits
 Combinational Circuit Testing
 Fault Model
 Path Sensitizing
 Random Test
 Sequential Circuit Testing
 Scan Path Test
 Built-in Self Test (BIST)
 Built-in Logic Block Observer (BIBLO)
 Signature Analyzer
 Boundary Scan Test (BST) 4

5. FAULT MODEL
 A circuit functions incorrectly when there is something wrong with
it, such as a transistor fault or an interconnection wiring fault.
 A transistor switch can break so that it is permanently either
closed or open.
 A wire in the circuit can be shorted to VDD or to ground, or it can
be simply broken.
 There can be an unwanted connection between two wires.
 Fortunately, it is possible to restrict the testing process to some
simple faults, and obtain generally satisfactory results.
5

6. STUCK AT MODEL
 A good model for representing faults is to assume that all faults
manifest themselves as some wires (inputs or outputs of gates)
being permanently stuck at logic value 0 or 1.
 Consider a wire, w.
 If w has an undesirable signal that always corresponds to the logic value
0, by saying that w is stuck-at-O, which is denoted as w/0.
 If w has an undesirable signal that is always equal to logic 1, then w is
stuck-at-1, which is denoted as w/1.
 A circuit can have either a single fault or possibly many faults.
Dealing with multiple faults is difficult because each fault can
occur in many different ways. A pragmatic (practical) approach is
to consider single faults only.
6

7. STUCK AT MODEL
7

8. PATH SENSITIZING
 Previous approach is not feasible from the practical point of view,
because if there are too many wires then it will have too many
faults.
 A better alternative is to deal with several wires that form a path
as an entity that can be tested for several faults using a single
test.
 It is possible to activate a path so that the changes in the signal
that propagates along the path have a direct impact on the output
signal.
8

9. PATH SENSITIZING
9
 The path is activated by ensuring that other paths in the circuit do
not determine the value of the output f.
 If w2 =1 then b depends only on the value a.
 If w3 = 0 so that it does not affect the NOR gate,
 If w4 =1 it not affect the AND gate.
 Then if w1 = 0 the output will be f = 1,
whereas w1 = 1 will cause f = 0.
Instead of saying that the path from w1 to f is activated, a more
specific term is used, which says that the path is sensitized.

10. PATH SENSITIZING
10
 To sensitize a path through an input of an AND or NAND gate, all
other inputs must be set to 1.
 To sensitize a path through an input of an OR or NOR gate, all
other inputs must be 0.

11. SCAN PATH TESTING
11

12. SCAN PATH TESTING
12
 Scan path, uses multiplexers on flip-flop
inputs to allow the flip-flops to be used
either independently during normal
operation of the sequential circuit, or as a
part of a shift register for testing purposes.
 Figure presents the general scan-path
structure for a circuit with three flip-flops.
 A 2-to-l multiplexer connects the D input of
each flip-flop either to the corresponding
next-state variable or to the serial path that
connects all flip-flops into a shift register.
 The control signal Normal/Scan selects the
active input of the multiplexer.
 During the normal operation the flip-flop
inputs are driven by the next-state
variables, Y1 , Y2, and Y3 •.

13. SCAN PATH TESTING
13
 For testing purposes the shift-register
connection is used to scan in the portion
of each test vector that involves the
present-state variables, Y1, Y2, and Y3.
 This connection has Qi connected to
Di+1 .
 The input to the first flip-flop is the
externally accessible pin Scan-in.
 The output comes from the last flip-flop,
which is provided on the Scan-out pin.

14. SCAN PATH TESTING
 Example
14

15. BUILT-IN SELF TEST
15
 The circuit with self-testable facility, is called as built-in self-test
(BIST).
 Figure shows a possible BIST arrangement in which a test vector
generator produces the test vectors that must be applied to the
circuit under test (CUT).

16. BUILT-IN SELF TEST
 LFSR (Linear Feedback Shift Register)
16
The circuit in Figure is linear feedback shift registers (LFSRs).
Using feedback from the various stages of an n-bit shift register,
connected to the first stage by means of XOR gates, it is possible to
generate a sequence of 2n-1 patterns that have the characteristics of
randomly generated numbers.

17. BUILT-IN SELF TEST
17
 SIC (Single Input Compressor Circuit )

18. BUILT-IN SELF TEST
18
 MIC (Multiple Input Compressor Circuit)
Above figure illustrates how four inputs, P0 through P3, can be added to
the basic circuit of previous figure.
Again the four-bit signature provides a good mechanism for
distinguishing among different sequences of four-bit patterns that may
appear on the inputs of this multiple-input compressor circuit (MIC).

19. BUILT-IN SELF TEST
19
 MIC
(Multiple Input
Compressor
Circuit)
 SIC
(Single Input
Compressor
Circuit)
 PRBSG
(Pseudorandom
Binary
Sequence
Generator)

20. BUILT-IN SELF TEST
20
Example :
BIBLO: Built-In Logic Block Observer

21. BUILT-IN SELF TEST
21
Example :
Signature Analysis
 Signature Analysis using BIBLO

22. BOUNDARY SCAN TEST
 The testing techniques discussed in the previous
sections are equally applicable to circuits that are
implemented on single chips.
 A circuit can be tested only if it is possible to apply the
tests to it and observe the outputs produced.
 When chips are soldered onto a printed circuit board, it
often becomes impossible to attach test probes to pins.
 This obstructs the testing process unless some indirect
access to the pins is provided. The scan-path concept
can be extended to the board level to deal with the
problem.
22

23. BOUNDARY SCAN TEST
 Suppose that each primary input or output pin on a chip
is connected through a D flip-flop and that a provision is
made for a test mode in which all flip-flops can be
connected into a shift register.
 Then the test information can be scanned in and
scanned out using the shift-register path, via two pins
that serve as serial input and output.
 Connecting the serial output pin of one chip to the serial
input pin of another chip results in the pins of all chips
being connected into a board-wide shift register for
testing purposes. 23

24. VLSI DESIGN FLOW WITH REFERENCE TO XILINX TOOL
24

25. THANK YOU
25
shindesir.pvp@gmail.com
This presentation is published only for educational purpose