1. Lab 7: Page tables
Advanced Operating Systems
Zubair Nabi
zubair.nabi@itu.edu.pk
March 27, 2013

2. Introduction
Page tables allow the OS to:
• Multiplex the address spaces of different processes onto a single
physical memory space
• Protect the memories of different processes
• Map the same kernel memory in several address spaces
• Map the same user memory more than once in one address
space (user pages are also mapped into the kernel’s physical
view of memory)

3. Introduction
Page tables allow the OS to:
• Multiplex the address spaces of different processes onto a single
physical memory space
• Protect the memories of different processes
• Map the same kernel memory in several address spaces
• Map the same user memory more than once in one address
space (user pages are also mapped into the kernel’s physical
view of memory)

4. Introduction
Page tables allow the OS to:
• Multiplex the address spaces of different processes onto a single
physical memory space
• Protect the memories of different processes
• Map the same kernel memory in several address spaces
• Map the same user memory more than once in one address
space (user pages are also mapped into the kernel’s physical
view of memory)

5. Introduction
Page tables allow the OS to:
• Multiplex the address spaces of different processes onto a single
physical memory space
• Protect the memories of different processes
• Map the same kernel memory in several address spaces
• Map the same user memory more than once in one address
space (user pages are also mapped into the kernel’s physical
view of memory)

6. Introduction
Page tables allow the OS to:
• Multiplex the address spaces of different processes onto a single
physical memory space
• Protect the memories of different processes
• Map the same kernel memory in several address spaces
• Map the same user memory more than once in one address
space (user pages are also mapped into the kernel’s physical
view of memory)

7. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

8. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

9. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

10. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

11. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

12. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

13. Page table structure
• An x86 page table contains 220 page table entries (PTEs)
• Each PTE contains a 20-bit physical page number (PPN) and
some flags
• The paging hardware translates virtual addresses to physical
ones by:
Using the top 20 bits of the virtual address to index into the page
table to find a PTE
2 Replacing the top 20 bits with the PPN in the PTE
3 Copying the lower 12 bits verbatim from the virtual to the physical
address
1
• Translation takes place at the granularity of 212 byte (4KB)
chunks, called pages

14. Page table structure (2)
• A page table is stored in physical memory as a two-level tree
• Root of the tree: 4KB page directory
• Each page directory index: page table pages (PDE)
• Each page table page: 1024 32-bit PTEs
• 1024 x 1024 = 220

15. Page table structure (2)
• A page table is stored in physical memory as a two-level tree
• Root of the tree: 4KB page directory
• Each page directory index: page table pages (PDE)
• Each page table page: 1024 32-bit PTEs
• 1024 x 1024 = 220

16. Page table structure (2)
• A page table is stored in physical memory as a two-level tree
• Root of the tree: 4KB page directory
• Each page directory index: page table pages (PDE)
• Each page table page: 1024 32-bit PTEs
• 1024 x 1024 = 220

17. Page table structure (2)
• A page table is stored in physical memory as a two-level tree
• Root of the tree: 4KB page directory
• Each page directory index: page table pages (PDE)
• Each page table page: 1024 32-bit PTEs
• 1024 x 1024 = 220

18. Page table structure (2)
• A page table is stored in physical memory as a two-level tree
• Root of the tree: 4KB page directory
• Each page directory index: page table pages (PDE)
• Each page table page: 1024 32-bit PTEs
• 1024 x 1024 = 220

19. Translation
• Use top 10 bits of the virtual address to index the page directory
• If the PDE is present, use next 10 bits to index the page table
page and obtain a PTE
• If either the PDE or the PTE is missing, raise a fault
• This two-level structure increases efficiency
• How?

20. Translation
• Use top 10 bits of the virtual address to index the page directory
• If the PDE is present, use next 10 bits to index the page table
page and obtain a PTE
• If either the PDE or the PTE is missing, raise a fault
• This two-level structure increases efficiency
• How?

21. Translation
• Use top 10 bits of the virtual address to index the page directory
• If the PDE is present, use next 10 bits to index the page table
page and obtain a PTE
• If either the PDE or the PTE is missing, raise a fault
• This two-level structure increases efficiency
• How?

22. Translation
• Use top 10 bits of the virtual address to index the page directory
• If the PDE is present, use next 10 bits to index the page table
page and obtain a PTE
• If either the PDE or the PTE is missing, raise a fault
• This two-level structure increases efficiency
• How?

23. Permissions
Each PTE contains associated flags
Flag
PTE_P
PTE_W
PTE_U
PTE_PWT
PTE_PCD
PTE_A
PTE_D
PTE_PS
Description
Whether the page is present
Whether the page can be written to
Whether user programs can access the page
Whether write through or write back
Whether caching is disabled
Whether the page has been accessed
Whether the page is dirty
Page size

24. Process address space
• Each process has a private address space which is switched on a
context switch (via switchuvm)
• Each address space starts at 0 and goes up to KERNBASE
allowing 2GB of space (specific to xv6)
• Each time a process requests more memory, the kernel:
Finds free physical pages
Adds PTEs that point to these physical pages in the process’ page
table
3 Sets PTE_U, PTE_W, and PTE_P
1
2

25. Process address space
• Each process has a private address space which is switched on a
context switch (via switchuvm)
• Each address space starts at 0 and goes up to KERNBASE
allowing 2GB of space (specific to xv6)
• Each time a process requests more memory, the kernel:
Finds free physical pages
Adds PTEs that point to these physical pages in the process’ page
table
3 Sets PTE_U, PTE_W, and PTE_P
1
2

26. Process address space
• Each process has a private address space which is switched on a
context switch (via switchuvm)
• Each address space starts at 0 and goes up to KERNBASE
allowing 2GB of space (specific to xv6)
• Each time a process requests more memory, the kernel:
Finds free physical pages
Adds PTEs that point to these physical pages in the process’ page
table
3 Sets PTE_U, PTE_W, and PTE_P
1
2

27. Process address space
• Each process has a private address space which is switched on a
context switch (via switchuvm)
• Each address space starts at 0 and goes up to KERNBASE
allowing 2GB of space (specific to xv6)
• Each time a process requests more memory, the kernel:
Finds free physical pages
Adds PTEs that point to these physical pages in the process’ page
table
3 Sets PTE_U, PTE_W, and PTE_P
1
2

28. Process address space
• Each process has a private address space which is switched on a
context switch (via switchuvm)
• Each address space starts at 0 and goes up to KERNBASE
allowing 2GB of space (specific to xv6)
• Each time a process requests more memory, the kernel:
Finds free physical pages
Adds PTEs that point to these physical pages in the process’ page
table
3 Sets PTE_U, PTE_W, and PTE_P
1
2

29. Process address space
• Each process has a private address space which is switched on a
context switch (via switchuvm)
• Each address space starts at 0 and goes up to KERNBASE
allowing 2GB of space (specific to xv6)
• Each time a process requests more memory, the kernel:
Finds free physical pages
Adds PTEs that point to these physical pages in the process’ page
table
3 Sets PTE_U, PTE_W, and PTE_P
1
2

30. Process address space (2)
Each process’ address space also contains mappings (above
KERNBASE) for the kernel to run. Specifically:
• KERNBASE:KERNBASE+PHYSTOP is mapped to 0:PHYSTOP
• The kernel can use its own instructions and data
• The kernel can directly write to physical memory (for instance,
when creating page table pages)
• A shortcoming of this approach is that the kernel can only make
use of 2GB of memory
• PTE_U is not set for all entries above KERNBASE

31. Process address space (2)
Each process’ address space also contains mappings (above
KERNBASE) for the kernel to run. Specifically:
• KERNBASE:KERNBASE+PHYSTOP is mapped to 0:PHYSTOP
• The kernel can use its own instructions and data
• The kernel can directly write to physical memory (for instance,
when creating page table pages)
• A shortcoming of this approach is that the kernel can only make
use of 2GB of memory
• PTE_U is not set for all entries above KERNBASE

32. Process address space (2)
Each process’ address space also contains mappings (above
KERNBASE) for the kernel to run. Specifically:
• KERNBASE:KERNBASE+PHYSTOP is mapped to 0:PHYSTOP
• The kernel can use its own instructions and data
• The kernel can directly write to physical memory (for instance,
when creating page table pages)
• A shortcoming of this approach is that the kernel can only make
use of 2GB of memory
• PTE_U is not set for all entries above KERNBASE

33. Process address space (2)
Each process’ address space also contains mappings (above
KERNBASE) for the kernel to run. Specifically:
• KERNBASE:KERNBASE+PHYSTOP is mapped to 0:PHYSTOP
• The kernel can use its own instructions and data
• The kernel can directly write to physical memory (for instance,
when creating page table pages)
• A shortcoming of this approach is that the kernel can only make
use of 2GB of memory
• PTE_U is not set for all entries above KERNBASE

34. Process address space (2)
Each process’ address space also contains mappings (above
KERNBASE) for the kernel to run. Specifically:
• KERNBASE:KERNBASE+PHYSTOP is mapped to 0:PHYSTOP
• The kernel can use its own instructions and data
• The kernel can directly write to physical memory (for instance,
when creating page table pages)
• A shortcoming of this approach is that the kernel can only make
use of 2GB of memory
• PTE_U is not set for all entries above KERNBASE

35. Process address space (2)
Each process’ address space also contains mappings (above
KERNBASE) for the kernel to run. Specifically:
• KERNBASE:KERNBASE+PHYSTOP is mapped to 0:PHYSTOP
• The kernel can use its own instructions and data
• The kernel can directly write to physical memory (for instance,
when creating page table pages)
• A shortcoming of this approach is that the kernel can only make
use of 2GB of memory
• PTE_U is not set for all entries above KERNBASE

36. Example: Creating an address space for main
• main makes a call to kvmalloc
• kvmalloc creates a page table with kernel mappings above
KERNBASE and switches to it
1
2
3
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5
void kvmalloc (void)
{
kpgdir = setupkvm ();
switchkvm ();
}

37. Example: Creating an address space for main
• main makes a call to kvmalloc
• kvmalloc creates a page table with kernel mappings above
KERNBASE and switches to it
1
2
3
4
5
void kvmalloc (void)
{
kpgdir = setupkvm ();
switchkvm ();
}

38. Example: Creating an address space for main
• main makes a call to kvmalloc
• kvmalloc creates a page table with kernel mappings above
KERNBASE and switches to it
1
2
3
4
5
void kvmalloc (void)
{
kpgdir = setupkvm ();
switchkvm ();
}

39. setupkvm
1
Allocates a page of memory to hold the page directory
2
Calls mappages to install kernel mappings (kmap)
• Instructions and data
• Physical memory up to PHYSTOP
• Memory ranges for I/O devices
Does not install mappings for user memory

40. setupkvm
1
Allocates a page of memory to hold the page directory
2
Calls mappages to install kernel mappings (kmap)
• Instructions and data
• Physical memory up to PHYSTOP
• Memory ranges for I/O devices
Does not install mappings for user memory

41. setupkvm
1
Allocates a page of memory to hold the page directory
2
Calls mappages to install kernel mappings (kmap)
• Instructions and data
• Physical memory up to PHYSTOP
• Memory ranges for I/O devices
Does not install mappings for user memory

42. setupkvm
1
Allocates a page of memory to hold the page directory
2
Calls mappages to install kernel mappings (kmap)
• Instructions and data
• Physical memory up to PHYSTOP
• Memory ranges for I/O devices
Does not install mappings for user memory

43. setupkvm
1
Allocates a page of memory to hold the page directory
2
Calls mappages to install kernel mappings (kmap)
• Instructions and data
• Physical memory up to PHYSTOP
• Memory ranges for I/O devices
Does not install mappings for user memory

44. setupkvm
1
Allocates a page of memory to hold the page directory
2
Calls mappages to install kernel mappings (kmap)
• Instructions and data
• Physical memory up to PHYSTOP
• Memory ranges for I/O devices
Does not install mappings for user memory

45. Code: kmap
1
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11
static struct kmap {
void
∗virt;
uint phys_start ;
uint phys_end ;
int perm;
} kmap [] = {
{ (void ∗)KERNBASE , 0, EXTMEM , PTE_W }, // I/O space
{ (void ∗)KERNLINK , V2P( KERNLINK ), V2P(data), 0}, // kern text
{ (void ∗)data , V2P(data), PHYSTOP , PTE_W }, // kern data
{ (void ∗)DEVSPACE , DEVSPACE , 0, PTE_W }, // more devices
};

46. Code: setupkvm
1
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pde_t∗ setupkvm (void) {
pde_t
∗pgdir ;
∗k;
struct kmap
if(( pgdir = ( pde_t ∗)kalloc ()) == 0)
return 0;
memset (pgdir , 0, PGSIZE );
for(k = kmap; k < &kmap[ NELEM (kmap )]; k++)
if( mappages (pgdir , k−>virt , k−>phys_end
− k−>phys_start ,
(uint)k−>phys_start , k−>perm) < 0)
return 0;
return pgdir ;
}

47. mappages
• Installs virtual to physical mappings for a range of addresses
• For each virtual address:
1 Calls walkpgdir to find address of the PTE for that address
2
Initializes the PTE with the relevant PPN and the desired
permissions

48. mappages
• Installs virtual to physical mappings for a range of addresses
• For each virtual address:
1 Calls walkpgdir to find address of the PTE for that address
2
Initializes the PTE with the relevant PPN and the desired
permissions

49. mappages
• Installs virtual to physical mappings for a range of addresses
• For each virtual address:
1 Calls walkpgdir to find address of the PTE for that address
2
Initializes the PTE with the relevant PPN and the desired
permissions

50. mappages
• Installs virtual to physical mappings for a range of addresses
• For each virtual address:
1 Calls walkpgdir to find address of the PTE for that address
2
Initializes the PTE with the relevant PPN and the desired
permissions

51. walkpgdir
1
Uses the upper 10 bits of the virtual address to find the PDE
2
Uses the next 10 bits to find the PTE

52. walkpgdir
1
Uses the upper 10 bits of the virtual address to find the PDE
2
Uses the next 10 bits to find the PTE

53. Physical memory allocation
• Physical memory between the end of the kernel and PHYSTOP is
allocated on the fly
• Free pages are maintained through a linked list struct run
*freelist protected by a spinlock
1 Allocation: Remove a page from the list: kalloc()
2 Deallocation: Add the page to the list: kfree()
1
2
3
4
5
struct {
struct spinlock lock;
int use_lock ;
struct run
} kmem;
∗freelist ;

54. Physical memory allocation
• Physical memory between the end of the kernel and PHYSTOP is
allocated on the fly
• Free pages are maintained through a linked list struct run
*freelist protected by a spinlock
1 Allocation: Remove a page from the list: kalloc()
2 Deallocation: Add the page to the list: kfree()
1
2
3
4
5
struct {
struct spinlock lock;
int use_lock ;
struct run
} kmem;
∗freelist ;

55. Physical memory allocation
• Physical memory between the end of the kernel and PHYSTOP is
allocated on the fly
• Free pages are maintained through a linked list struct run
*freelist protected by a spinlock
1 Allocation: Remove a page from the list: kalloc()
2 Deallocation: Add the page to the list: kfree()
1
2
3
4
5
struct {
struct spinlock lock;
int use_lock ;
struct run
} kmem;
∗freelist ;

56. Physical memory allocation
• Physical memory between the end of the kernel and PHYSTOP is
allocated on the fly
• Free pages are maintained through a linked list struct run
*freelist protected by a spinlock
1 Allocation: Remove a page from the list: kalloc()
2 Deallocation: Add the page to the list: kfree()
1
2
3
4
5
struct {
struct spinlock lock;
int use_lock ;
struct run
} kmem;
∗freelist ;

57. Physical memory allocation
• Physical memory between the end of the kernel and PHYSTOP is
allocated on the fly
• Free pages are maintained through a linked list struct run
*freelist protected by a spinlock
1 Allocation: Remove a page from the list: kalloc()
2 Deallocation: Add the page to the list: kfree()
1
2
3
4
5
struct {
struct spinlock lock;
int use_lock ;
struct run
} kmem;
∗freelist ;

58. exec
• Creates the user part of an address space from the program
binary, in Executable and Linkable Format (ELF)
• Initializes instructions, data, and stack

59. exec
• Creates the user part of an address space from the program
binary, in Executable and Linkable Format (ELF)
• Initializes instructions, data, and stack

60. Today’s task
• Most operating systems implement “anticipatory paging” in which
on a page fault, the next few consecutive pages are also loaded
to preemptively reduce page faults
• Chalk out a design to implement this strategy in xv6

61. Reading(s)
• Chapter 2, “Page tables” from “xv6: a simple, Unix-like teaching
operating system”