Architecture of 8086

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2. Features of 8086 Processor
 8086 is a 16-bit microprocessor
 16 bit data bus
 20 bit address bus
 8086 can generate 16 bit I/O address
 Fourteen 16 bit registers
 Multiplexed address and data bus which reduces the
number of pin needed but slow down the transfer of
data
 Perform bit, byte, word and block operations
 Arithmetic and logical operations on bit, byte, word
and decimal.
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3. The 8086 Processor Model
Block Diagram of 8086
• The simplified block diagram of the 80x86 processor model is organized as two
separate processors:
•Bus Interface Unit(BIU)
•Execution Unit(EU).
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4. Block Diagram of 8086
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The 8086 Processor Architecture

5. The 8086 Processor Model
Functions Of Bus interface Unit :
 It sends address of the memory or I/O.
 It fetches instruction from memory.
 It reads data from port/memory.
 It writes data into port/memory.
 It supports instruction queuing.
 It provides the address relocation facility.
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6. The 8086 Processor Model
 The BIU provides hardware functions. Including generation of the
memory and I/O addresses for the transfer of data between itself and the
outside world.
 The EU receives program instruction codes and data from the BIU
,executes these instructions, and stores the results in the general
registers. By passing the data back to the BIU,data can also be stored
in a memory location or written to an output device.
 The main linkage between the two functional blocks is the instruction
queue, with the BIU looking ahead of the current instruction being executed
in order to keep the queue filled with instructions for the EU to decode and
operate on.
 The EU has no connection to the system buses. It receives and outputs all of its
data through the BIU.
 The execution unit, or EU, handles the arithmetic and logical operations on the
data and has a 6-byte first-in, first-out(FIFO)instruction queue.
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7. The 8086 Processor Model
The Fetch and Execute Cycle:
 The organization of the processor into a separate BIU and EU allows the fetch and
execute cycles to overlap.
 To see this, consider what happens when the 8086 is first started.
1. The BIU outputs the contents of the instruction pointer register(IP) onto the address bus,
causing the selected byte or word in memory to be read into the BIU.
2. Register IP is incremented by one to prepare for the next instruction fetch.
3. Once inside the BIU , the instruction is passed to the queue: a first-in/first-out storage
register sometimes likened to a pipeline.
4. Assuming that the queue is initially empty, the EU immediately draws this instruction
from the queue and begins execution.
5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.
Depending on the execution time of the first instruction, the BIU may fill the queue with
several new instructions before the EU is ready to draw its next instruction.
6. The cycle continues, with the BIU filling the queue with instructions and the EU fetching
and executing these instructions.
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8. The 8086 Processor Model
The Fetch and Execute Cycle (contd.)
 The BIU is programmed to fetch a new instruction whenever the queue has room for two
additional bytes.
 The advantage to this pipelined architecture is that the EU can execute
instructions(almost) continually instead of having to wait for the BIU to fetch a new
instruction.
 This is shown schematically in the following Figure
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9. The 8086 Processor Model
 The “Wait” mode :
 There are three conditions that will cause the EU to enter a
"wait" mode.
 When an instruction requires access to a memory location. The
BIU must suspend fetching instructions and output the address of
this memory location. After waiting for the memory access, the
EU can resume executing instruction codes from the queue, and
the BIU can resume filling the queue.
 When the instruction to be executed is a jump instruction. In this
case, control is to be transferred to a new address. The EU must
wait while the instruction at the jump address is fetched. Any
bytes presently in the queue must be discarded (they are
overwritten).
 During the execution of slow-executing instructions.
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10. The 8086 Processor Model
What About the 8088?
 The only significant difference between the 8088
microprocessor and the 8086 microprocessor is the BIU.
 In the 8088,the BIU data bus path is 8 bits wide Where the
8086 BIU data bus is l6 bit. Another difference is that the 8088
instruction queue is four bytes long instead of six.
 In practice ,however, the 8088 is found to only be about 30
percents slower than an 8086.
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