40. Most electronic ballasts and switching power supplies use a bridge rectifier and a
bulk storage capacitor to derive raw dc voltage from the utility ac line, figure above:
Vin=100Vac, 50Hz and PO=200W.
Copyright (C) Bee Technologies Inc. 2013 40
Vin
AC_IN1
PARAMETERS:
f req = 50Hz
Vin = 100Vac
AC_IN2
Cbulk
2000uF
0
bulkDB1
DB2DB3
Diode
DB4
Load
1.414Adc
Iline
Vbulk
3.1.3 電流臨界モード方式PFC制御回路
41. Time
160ms 164ms 168ms 172ms 176ms 180ms 184ms 188ms 192ms 196ms 200ms
AVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
0
0.2
0.4
0.6
0.8
1.0
ABS( I(Vin) )
0A
10A
20A
ABS( V(AC_IN1,AC_IN2) ) V(bulk)
0V
100V
200V
SEL>>
The Uncorrected Power Factor rectifying circuit draws current from the ac line when the
ac voltage exceeds the capacitor voltage (Vbulk). The current (Iline) is non-sinusoidal. This
results in a poor power factor condition where the apparent input power is much higher
than the real power, figure above, power factor ratios of 0.5 to 0.7 are common.
Copyright (C) Bee Technologies Inc. 2013 41
|VAC, in, 100V| (VPEAK, in=100*2=141.42V) and Vbulk
|Iline|
Power Factor Ratio = Pin, avg./(Vin, rms* Iin, rms)
3.1.3 電流臨界モード方式PFC制御回路
42. Vac, in
C1
1uF
C2
200u
ILoad
0.5A
L1
12
Diode
D2
Q1
MOSFET
R7
L2
1 2
0
0
Rectifiers PFC
TB6819AFG
Controller
Circuit
PARAMETERS:
f req = 50Hz
Vin = 100Vac
The Power Factor Correction (PFC) circuit, as an off-line active preconverter, is designed to
draw a sinusoidal current from the AC line that is in phase with input voltage. As a result, the
power factor ratio is improved to be near to ideal (1).
The TB6819AFG is a critical conduction mode (CRM) PFC controller IC. The description
including equation and constants as a guide to understand its designing process is included in
this document.
Copyright (C) Bee Technologies Inc. 2013 42
Iline
VDC, OUT
3.1.3 電流臨界モード方式PFC制御回路
43. Time*10
100ms 104ms 108ms 112ms 116ms 120ms 124ms 128ms 132ms 136ms 140ms
AVG(ABS(W(Vin))) / (RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
0
0.2
0.4
0.6
0.8
1.0
-I(Vin)
-8.0A
0A
8.0A
SEL>>
1 V(AC_IN1,AC_IN2) 2 V(VOUT)
-160V
0V
160V
1
200V
400V
600V
2
>>
The poor power factor load is corrected by keeping the ac line current sinusoidal and in phase
with the line voltage. This results with power factor ratio is 0.85.
Copyright (C) Bee Technologies Inc. 2013 43
VAC, in, 100V and VDC, OUT, 400V
Iline
Power Factor Ratio = 0.85
*simulation result at tscale = 10
3.1.3 電流臨界モード方式PFC制御回路
47. Time
476us 480us 484us 488us 492us 496us 500us 504us 508us 512us 516us
V(V2)
0V
40V
-I(L1)
0A
5A
10A
V(V1)
0V
250V
500V
V(Q1:g)
10V
20V
SEL>>
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(VOUT)
392V
400V
Copyright (C) Bee Technologies Inc. 2013 47
The Simulation Waveform with the defaults models
V(V1)
I (L1)
V(V2)
V(VOUT) without high frequency ripple which is caused by ESR and ESL of the capacitor model.
Gate charge characteristics is not include in the default model.
Total simulation time = 132.41 seconds
3.1.3 電流臨界モード方式PFC制御回路
48. Load
0.5A
R12
39k
Q2
2SK2611
C9
0.1uF
Vin
FREQ = {f req*tscale}
VAMPL = {Vin*1.414}
AC_IN1
R4 100
PARAMETERS:
f req = 50
Vin = 100
C6 3300p
AC_IN2
C1
1u
0
0
R9
3MEG
R10
22k
C5
{10n/tscale}
C8
47uF
IC = 17.9
D5
DZ18V
R11
360k
R6
68k
R8
100k
MULT
Rtf
C3
{0.47u/tscale}
IC = 3.74
L1
{L}
12
PARAMETERS:
L = 230u
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
VCC
V1
R7
0.11
POUT
V2
U1
TB6819AFG
FB_IN
COMP
MULT
ISZCD
GND
POUT
VCC
FB_IN
ISZCD
C7
8p
R3
10k
C4
{1u/tscale}
VOUT
R2
1.5MEG
R1
9.53k
COMP
L2
{N*N*L}
1 2
K
K1
COUPLING = 1
K_Linear
L1 = L1
L2 = L2
C2
RJJ-35V221MG5-T20
D2
SCS110AG
DB1
Diode
D3
Diode
D4
PARAMETERS:
tscale = 10
DB2DB3
Diode
DB4
R5
10
Simulation with Models from the SpicePark
Copyright (C) Bee Technologies Inc. 2013 48
Capacitor
model
MOSFET
professional
model
Schottky diode
model
Replace some default model with models from SpicePark
*Analysis directives:
.TRAN 0 2ms 0 100n
.OPTIONS ABSTOL= 100n
.OPTIONS GMIN= 1.0E-8
.OPTIONS ITL1= 500
.OPTIONS ITL2= 200
.OPTIONS ITL4= 100
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 100u
3.1.3 電流臨界モード方式PFC制御回路
49. Time
484us 488us 492us 496us 500us 504us 508us 512us 516us 520us 524us
V(V2)
0V
40V
-I(L1)
0A
5A
10A
V(V1)
0V
250V
500V
V(Q2:g)
10V
20V
SEL>>
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(VOUT)
392V
400V
Simulation with Models from the SpicePark
Copyright (C) Bee Technologies Inc. 2013 49
V(VOUT) with high frequency ripple which is caused by ESR and ESL of the capacitor model.
Gate charge characteristics is include in the MOSFET Professional model.
V(V1)
I (L1)
V(V2)
Total simulation time = 408.13 seconds
3.1.3 電流臨界モード方式PFC制御回路
61. +
-
SPEAKER
F120A
FET1
IRFIZ24N
FET2
IRFIZ24N
+
C1
EKMG500ELL100ME11D
C6
AMZ0050J102C3
RPER11H103K2K1A01B
V1
FREQ = {f in}
VAMPL = { 1.4142*VOUT/Gv }
VOFF = 0
0
C4
1nF
+B
15V
+
C18
EKMG500ELL222MLP1S
C5
1nF
0
R18
10
0
R19
2.2k
C14
MMH250K684
R4
220
C7
10u
IC = 10
R2
3k
R1
100k
C10 22u
IC = 15
OUT
C9
22u
IC = 12.85
MUR120RLG
D2
VS
IN
R13
10
R3
47k
L1
7G14N-220-RB
VB
R17
1
0
R20
3.3k
R21
8.2k
R8
820
+B
VREF
VAA
0
R6 8.2k
R7
1.2k
CSD
OCSET
IN-
IC1
IRS2092
VAA
GND
IN-
COMP
CSD
VSS
VREF
OCSET DT
COM
LO
VCC
VS
HO
VB
CSH
VCC
0
DT
VSS 0
COMP
HO
R5
820
-B
R15
10
LO
VR1
75
-B
-15V
0
C2
10u
IC = 7
C8
10u
IC = 7
R11
10k
CSH
VS
C13
MMC400K104
0
C12
MMC250K474
R16
10
C11
RPER11H104K2K1A01B
C15
RPER11H104K2K1A01B
0Ls1
20nH
1
2
Ls2
20nH
1
2
Ls3
20nH
1
2
Ls4
20nH
1
2
R14
4.7
MUR120RLG
D1
0
R9
4.7k
+
C16
EKMG500ELL222MLP1S
Ls5
20nH
12
C17
RPER11H104K2K1A01B
R12
10k
PARAMETERS:
VOUT = 2
Gv = 15.85
f in = 1k
V
V
V
V V
V
61
Time
505.0us 510.0us
V(VS)
-40V
0V
40V
Time
505.0us 510.0us
V(HO)
-40V
0V
40V
Time
505us 510us503us 513us
V(LO)
-20V
0V
Time
0.50ms 0.75ms 1.00ms 1.25ms
V(IN)
0V
-200mV
200mV
Time
505.0us 510.0us
V(COMP)
0V
-1.0V
1.0V
Class D amplifier circuit are simulated and compared with measured waveforms from oscilloscope
(Tektronix: TDS3054B)
Time
0s 0.3ms 0.7ms
V(OUT)
-4.0V
0V
4.0V
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
62. 62
Time
1.988ms 1.990ms 1.992ms 1.994ms 1.996ms 1.998ms
V(VS)
-40V
-30V
-20V
-10V
0V
10V
20V
30V
40V
OUT
VS
Simulated Measured
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
63. 63
Time
1.988ms 1.990ms 1.992ms 1.994ms 1.996ms 1.998ms
V(HO)
-40V
-30V
-20V
-10V
0V
10V
20V
30V
40V
Time
1.992ms 1.994ms 1.996ms 1.998ms 2.000ms 2.002ms
V(LO)
-40V
-30V
-20V
-10V
0V
10V
20V
30V
40V
HO
LO
Simulated Measured
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
64. 64
Self-oscillation frequency
= 400kHz (Simulated)
Self-oscillation frequency
= 400kHz (Measured)
Simulated Measured
OUT OUT
VS VS
Self-Oscillating Frequency
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
68. +
C1
EKMG500ELL100ME11D
C6
AMZ0050J102C3
RPER11H103K2K1A01B
C17
RPER11H104K2K1A01B
+
C18
EKMG500ELL222MLP1S
FET1
IRFIZ24N
FET2
IRFIZ24N
+
-
SPEAKER
F120A
0
C4
1nF
+B
15V
C5
1nF
0
R18
10
0
R19
2.2k
C14
MMH250K684
R4
220
C7
10u
IC = 10
R2
3k
R1
100k
C10 22u
IC = 15
OUT
C9
22u
IC = 12.85
MUR120RLG
D2
VS
IN
R13
10
R3
47k
L1
7G14N-220-RB
VB
R17
1
0
R20
3.3k
R21
8.2k
R8
820
+B
VREF
VAA
0
R6 8.2k
R7
1.2k
CSD
OCSET
IN-
IC1
IRS2092
VAA
GND
IN-
COMP
CSD
VSS
VREF
OCSET DT
COM
LO
VCC
VS
HO
VB
CSH
V1
FREQ = 1k
VAMPL = 0
VOFF = 0
VCC
0
DT
VSS 0
COMP
HO
R5
820
-B
R15
10
LO
VR1
75
-B
-15V
0
C2
10u
IC = 7
C8
10u
IC = 7
R11
10k
CSH
VS
C13
MMC400K104
0
C12
MMC250K474
R16
10
C11
RPER11H104K2K1A01B
C15
RPER11H104K2K1A01B
0Ls1
20nH
1
2
Ls2
20nH
1
2
Ls3
20nH
1
2
Ls4
20nH
1
2
R14
4.7
MUR120RLG
D1
0
R9
4.7k
+
C16
EKMG500ELL222MLP1S
Ls5
20nH
12
R12
10k
The total power loss in MOSFET are given by:
PTOTAL = PSW+Pcond+Pgd
68
Power losses in the MOSFETs
Analysis
Time Domain (Transient)
Run to time: 500us
Start saving data after: 100n
Maximum step size: 2n
Skip the initial transient bias point calculation (SKIPBP)
.Options
RELTOL: 0.003
VNTOL: 1.0m
ABSTOL: 100n
CHGTOL: 0.01p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
69. Time
23.6us 24.4us 25.2us 26.0us 26.8us 27.6us
1 V(FET1:S,FET1:D) 2 -I(Ls1) 3 V(FET1:D,FET1:S)*-I(Ls1)
0V
100V
-60V
1
-1.5A
-1.0A
-0.5A
0A
0.5A
1.0A
1.5A
2.0A
2.5A
2
>>
-50W
0W
20W
3
Power losses FET1(Professional Model)
69
FET1: ID and VDS are simulated and compared with scope (Tektronix: TDS3054B) waveforms
PSW ,Pcond ,and Pgd are calculated by PSpice.
VDS, ID (Measured)
-VDS
ID
-VDS
ID
Power loss (VDS*ID)
PSWPgd Pcond
VDS, ID (Simulated)
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
70. Time
492.8us 493.6us 494.4us 495.2us 496.0us
1 V(FET2:D,FET2:S) 2 -I(Ls3:1) 3 V(FET2:D,FET2:S)*-I(Ls3:1)
0V
100V
-40V
1
-1.0A
-0.5A
0A
0.5A
1.0A
1.5A
2.0A
2.5A
3.0A
2
>>
-50W
0W
20W
3
Power losses FET2(Professional Model)
70
FET2: ID and VDS are simulated and compared with scope (Tektronix: TDS3054B) waveforms
PSW ,Pcond ,and Pgd are calculated by PSpice.
VDS
ID
VDS
ID
Power loss (VDS*ID)
PSWPgd Pcond
VDS, ID (Measured)VDS, ID (Simulated)
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
71. • Gate charge characteristics in Professional model has more accurate results than standard model.
FET: IRFIZ24N Qg Standard vs. Professional Model
71
IRFIZ24N
(Standard)
IRFIZ24N
(Professional)
VDD=44V,ID=10A
,VGS=10V
Measurement Simulation Error (%)
Standard Model: Qg(nc) 13.400 12.543 -6.396
Professional Model: Qg(nc) 13.400 13.409 0.067
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
72. Time
867us 869us 871us 873us 875us 877us
1 V(OUT) 2 V(VS)
-1.0V
-0.5V
0V
0.5V
1.0V
1.5V
2.0V
2.5V
3.0V
1
>>
-120V
-80V
-40V
0V
40V
2
72
Simulated (without output capacitor models) Measured
OUT OUT
VS VS
Self-oscillation frequency
= 400kHz (Simulated)
Self-oscillation frequency
= 400kHz (Measured)
Simulation Result (without Capacitor Model)
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
73. 73
Simulated (with output capacitor models) Measured
OUT OUT
VS VS
Self-oscillation frequency
= 400kHz (Simulated)
Self-oscillation frequency
= 400kHz (Measured)
Simulation Result (with Capacitor Model)
Copyright (C) Bee Technologies Inc. 2013
3.2 D級アンプ
76. Full Step Switching Sequence
Copyright (C) Bee Technologies Inc. 2013 76
• This figure shows the simulation result of the circuit with Full-
step switching sequence.
Phase A
Phase B
Enable A
Enable B
IOUT A
IOUT B
Time
0s 4.0ms 8.0ms
I(U1:OUT_B1)
-1.0A
0A
1.0A
I(U1:OUT_A1)
-1.0A
0A
1.0A
V(U1:ENABLE_B)
0V
SEL>>
V(U1:ENABLE_A)
0V
V(PH_B)
0V
V(PH_A)
0V
3.3.1 ステッピングモータ制御回路
77. Time
2.54ms 2.58ms
I(U1:OUT_B1)
400mA
600mA
I(U1:OUT_A1)
400mA
600mA
SEL>>
Output Ripple Current
• This figure shows the output ripple current of the Mixed Decay Mode ,which consist of
Charge ,Slow decay ,and Fast decay mode ,with 101kHz chopping frequency.
Copyright (C) Bee Technologies Inc. 2013 77
IOUT = 0.5A
fchop = 101kHz
IOUT A
IOUT B
Charge mode
Slow decay mode Fast decay mode
3.3.1 ステッピングモータ制御回路
78. Time
2.593ms 2.595ms 2.597ms 2.599ms 2.601ms 2.603ms
I(U1:OUT_A1)
300mA
400mA
500mA
600mA
700mA
SEL>> Ripple Current Simulation
• The simulation result shows the current ripple that agrees to the measurement data.
Copyright (C) Bee Technologies Inc. 2013 78
Current ripple
Current ripple
Simulation
Measurement
3.3.1 ステッピングモータ制御回路
79. Parameter Settings
If there is no measurement data, the default value will be
used:
Rm: motor winding resistance []
Lm: motor winding inductance [H]
Data is given by D.C. motor spec-sheet:
V_norm: normal voltage [V]
mNm: normal load [mNm]
kRPM_norm: speed at normal load [kr/min]
I_norm: current at normal load [A]
Load Condition:
IL: load current [A]
Copyright (C) Bee Technologies Inc. 2013 79
Model Parameters:
D.C. Motor model and Parameters with Default Value
-
+
U1
SMPL_DC_MOTOR
Rm = 0.1
Lm = 100u
I_norm = 6.1
mNm = 19.6
V_norm = 7.2
kRPM_norm = 14.4
IL = 6.1
3.3.2 DCモータ制御回路
80. Copyright (C) Bee Technologies Inc. 2013 80
Time
0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms 360ms 400ms
I(VIM)
0A
10A
20A
V(VM)
0V
5V
10V
SEL>>
I(X_U1.V_kRPM)
0A
10A
20A
V(X_U1.TRQ)
0V
40V
80V
D.C. Motor Current = 6.1A
D.C. Motor Voltage = 7.2V
D.C. Motor Speed = 14.4krpm
Torque Load= 19.6mNm
3.3.2 DCモータ制御回路
81. Time
0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms 360ms 400ms
I(VIM)
0A
10A
20A
V(VM)
0V
5V
10V
I(X_U1.V_kRPM)
0A
10A
20A
SEL>>
V(X_U1.TRQ)
0V
40V
80V
Copyright (C) Bee Technologies Inc. 2013 81
D.C. Motor Current = 3.05A
D.C. Motor Voltage = 8.725V
D.C. Motor Speed = 18.4krpm
Torque Load= 9.8mNm
3.3.2 DCモータ制御回路
82. -
+
U2
SMPL_DC_MOTOR
Rm = 0.576
Lm = 165u
I_norm = 2.9
mNm = 9.8
V_norm = 7.2
kRPM_norm = 14.2
IL = 0.6
NC
NC
NCA
K
VCC
VO
GND
U1
TLP350
V1
TD = 0
TF = 10n
PW = 199.99u
PER = 400u
V1 = 0
TR = 10n
V2 = 1.8
0
R1
1u
0
Vcc
15V
0
VCC
VDD
0
RG
120
0
DGT10J321_s
D3
VCC
Vdd
15V
VDD
0
D4001
D2
U3
GT10J321
Copyright (C) Bee Technologies Inc. 2013 82
Simplified D.C. Motor with RS-
380PH Spec at No load.
Simulation Circuit and Setting
No load IL=0.6
Application Example
3.3.2 DCモータ制御回路
83. Time
-100ms 0s 100ms 300ms 500ms 700ms 900ms
1 I(U2:1) 2 V(U2:1,U2:2)
-2A
0A
2A
4A
6A
8A
10A
12A
14A
1
-60V
-50V
-40V
-30V
-20V
-10V
0V
10V
20V
2
>>
Application Example
Copyright (C) Bee Technologies Inc. 2013 83
Measurement Simulation
Motor Current (2A/Div)
Motor Voltage (10V/Div)
3.3.2 DCモータ制御回路