This document discusses the history and operation of transistors and their use in digital electronics. It begins with an overview of the bipolar junction transistor and field effect transistor. It then covers the different types of MOSFET transistors and their construction. The document explains how MOSFETs work and are used to implement logic gates in digital circuits. It provides examples of how to systematically design the pull-up and pull-down networks to realize Boolean logic functions using CMOS transistors.

1. The Revolution from Transistor to
Digital Electronics
PROJECT SUBMITTED BY:-
SAUPARNA DATTASAUPARNA DATTA
SUBHAJIT BHATTACHARJEESUBHAJIT BHATTACHARJEE

2. Table of Contents………
Bipolar Junction Transistor.
Field Effect Transistor.
MOSFET.
E-type MOSFET.
D-type MOSFET.
C-type MOSFET.
Entering into Digital Electronics
Logic Implementation.

3. History of transistors
In 1906, an American inventor and physicist, Lee De Forest, made the vacuum
tube triode or audion as he called it.
 Used in radios
 Used in early computers
In 1947, John Bardeen
and Walter Brattain
deviced - the first "point
contact" transistor.

4. Basic construction of Transistor

5. Transistor operation
force – voltage/current
water flow – current
- amplification

6. Field Effect Transistor
 Field effect Transistor is a semiconductor device which depends for its
operation on the control of current by an Electric Field.
 Classification of Field Effect Transistors

7. 7
7
Construction
Drain
Source
GATE
For a N
Channel FET
an N type
silicon Bar is
used
For a N
Channel FET
an N type
silicon Bar is
used
Heavily doped P
type material is
deposited on
either side of the
bar to form
GATE
Heavily doped P
type material is
deposited on
either side of the
bar to form
GATE
The two ends of
the bar are
known as Source
and Drain
The two ends of
the bar are
known as Source
and Drain
Fig 3. Construction of N Channel FET
EC-302.31 t0 32
AEI302.31 TO 33

8. Fig3116_new.swf

9. 9
9
Drain Characteristics
9
Drain characteristics show the relation between the
drain to source voltage and VDS and drain current ID
A
B
Avalanche BreakdownID
VDS
- VGS
OHMIC
Region Pinch Off
Region Breakdown Region
VGS= 0
AEI302.31 TO 33

10. MOSFET

11. How does a MOSFET work?
 Structure:
 Device formed on lightly
doped p-type substrate.
 Source and drain are heavily
doped with n-type.
 Oxide layer separates gate
from Si surface.
 Result: N-P-N type, nMOS.
nMOS device in enhancement mode
Equilibrium energy
band diagram
Operation: VGS > Vth

12. MOSFET
There are basically two types of Mosfet
Enhancement type Mosfet
Depletion type Mosfet

13. HELLO EVERY ONE LET’S LEARNHELLO EVERY ONE LET’S LEARN
VLSI BASIC BUILDING BLOCK…VLSI BASIC BUILDING BLOCK…
HELLO EVERY ONE LET’S LEARNHELLO EVERY ONE LET’S LEARN
VLSI BASIC BUILDING BLOCK…VLSI BASIC BUILDING BLOCK…
Fundamental of MOS TheoryFundamental of MOS Theory
andand
CMOS TransistorsCMOS Transistors

14. CMOS Transistor
Gate
Source
Drain
Gate
Drain
Source
Complementary MOS
 P-channel MOS (pMOS)
 N-channel MOS (nMOS)
pMOS
 P-type source and drain diffusions
 N substrate
 Mobility by holes
nMOS
 N-type source and drain diffusions
 P substrate
 Mobility by electrons
pMOS
nMOS

15. CMOS Transmission Gate
Transmit signal from INPUT to OUTPUT when
Gate is closed
Drain
Gate
INPUT
Gate (complementary of Gatecomplementary of Gate)
Gate pMOS nMOS OUTPUT
0 OFF OFF ZZ
1 ON ON INPUT
ZZ : High-Impedance State,
consider the terminal is “floating”

16. CMOS Inverter
Connect the following terminals of a PMOS and an NMOS
 Gates
 Drains
Vdd
PMOS
Vin Vout
Ground
NMOS
Vdd
Gnd
Vout
Vin
Vin
Vin = HIGH
Vout = LOW (Gnd)
ONON
OFFOFF
Vdd
Gnd
Vout
Vin
Vin
Vin = LOW
Vout = HIGH (Vdd)
ONON
OFFOFF

17. PUN/PDN of a CMOS Inverter
A B
0 1
1 Z
A B
0 Z
1 0
A B
0 1
1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
A
Gnd
B
CMOS Inverter

18. PUN/PDN of a NAND Gate
 A B C
0 0 1
0 1 1
1 0 1
1 1 Z
A B C
0 0 Z
0 1 Z
1 0 Z
1 1 0
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
A
B
A B
C
Vdd

19. PUN/PDN of a NOR Gate
A B C
0 0 1
0 1 Z
1 0 Z
1 1 Z
A B C
0 0 Z
0 1 0
1 0 0
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
A
C
B
A B
Vdd
A B C
0 0 1
0 1 0
1 0 0
1 1 0

20. PUN/PDN of a XOR Gate
Vdd
A
B
A A
A
B
B
B
C
A B C
0 0 Z
0 1 1
1 0 1
1 1 Z
A B C
0 0 0
0 1 Z
1 0 Z
1 1 0
A B C
0 0 0
0 1 1
1 0 1
1 1 0
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
Function = XORXOR

21. A Systematic Approach
Each variable in the given Boolean eqn corresponds
to a PMOS transistor in PUN and an NMOS
transistor in PDN
Draw PUNPUN using PMOS based on the Boolean eqn
 ANDAND operation drawn in seriesseries
 OROR operation drawn in parallelparallel
Invert each variablevariable of the Boolean eqn as the gate
input for each PMOS in the PUN
Draw PDNPDN using NMOS in complementary form
 Parallel (PUN) to series (PDN)
 Series (PUN) to parallel (PDN)
Label with the same inputs of PUN
Label the output

22. Example
BCAF +⋅=
In series
In parallel
Vdd
(1) Draw the Pull-Up Network

23. Example
BCAF +⋅=
In series
In parallel
Vdd
(2) Assign the complemented input
A
C
B

24. Example
BCAF +⋅=
In series
In parallel
Vdd
(3) Draw the Pull-Down Network in
the complementary form
A
C
B
A C

25. Example
BCAF +⋅=
In series
In parallel
Vdd
(3) Draw the Pull-Down Network in
the complementary form
A
C
B
A C
B

26. Example
BCAF +⋅=
In series
In parallel
Vdd
Label the output F
A
C
B
A C
B
F

27. Example
BCAF +⋅=
In series
In parallel
Vdd
A
C
B
A C
B
F
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
Truth Table

28. BIBLIOGRAPHY
Wikipedia.com
Google.com
Mahesh Naidu
(B.E. in Electrical & Electronics, BITS-Pilani Hyderabad Campus)