1. FLORIDA STATE UNIVERSITY
COLLEGE OF ENGINEERING
PERFORMANCE MODELING AND ANALYSIS OF
A CENTRALIZED FAULT LOCATION AND IDENTIFICATION SYSTEM
By
SHRAVAN TAMASKAR
A Thesis submitted to the
Department of Electrical and Computer Engineering
in partial fulfillment of the
requirements for the degree of
Master of Science
2016
2. ii
Shravan Tamaskar defended this thesis on June 06, 2016.
The members of the supervisory committee were:
Ming Yu
Professor Directing Thesis
Michael Steurer
Professor Co-Directing Thesis
Hui Li
Committee Member
The Graduate School has verified and approved the above-named committee members, and
certifies that the thesis has been approved in accordance with university requirements.
4. iv
ACKNOWLEDGMENTS
First of all, I would like to thank my research advisor Dr. Michael Steurer for allowing me a chance
to work on the project and being a part of the research team at Center for Advance Power System
(CAPS) at Florida State University and for his guidance and encouragement. I would also like to
thank my academic advisor Dr. Ming Yu for guiding me through the various challenges I faced in
the course of my thesis. I would also like to thank Dr. Helen Li to be a part of my thesis committee.
I would like to thanks Michael Sloderbeck, Harsha Ravindra, Mark Stanovich and Isaac Leonard
for their support, advice and suggestions that helped me in my thesis and also patiently discussion
about my work.
Last and the most important, I would like to thank my family for believing in me.
5. v
TABLE OF CONTENTS
List of Tables ................................................................................................................................ vii
List of Figures.............................................................................................................................. viii
List of Abbreviations .......................................................................................................................x
Abstract.......................................................................................................................................... xi
1. INTRODUCTION ......................................................................................................................1
1.1 Introduction..........................................................................................................................1
1.2 Motivation............................................................................................................................1
1.3 Literature review..................................................................................................................2
1.4 Outline..................................................................................................................................3
2. STRUCTURE OF CENTRALIZED FAULT LOCATION SYSTEM.......................................4
2.1 Protection of MVDC system................................................................................................4
2.2 Basic CFL architecture ........................................................................................................5
2.3 The CFL operation...............................................................................................................6
2.4 The CFL algorithm ..............................................................................................................9
2.5 Summary............................................................................................................................13
3. CFL COMMUNICATION SYSTEM.......................................................................................14
3.1 EtherCAT...........................................................................................................................14
3.2 Hardware............................................................................................................................16
3.3 Topology............................................................................................................................17
3.4 Modeling of an EtherCAT frame.......................................................................................18
3.5 Modeling of roundtrip communication cycle time ............................................................25
3.6 Decision time modeling.....................................................................................................28
3.6.1 RTDS processing ....................................................................................................30
3.6.2 Beckhoff processing................................................................................................31
3.6.3 Hardware synchronization ......................................................................................32
3.7 Factors affecting performance of CFL...............................................................................36
3.7.1 Topology .................................................................................................................36
3.7.2 Jitter.........................................................................................................................38
3.7.3 Bandwidth ...............................................................................................................39
3.7.4 Network propagation time.......................................................................................40
3.7.5 Noise .......................................................................................................................41
3.8 Summary............................................................................................................................51
6. vi
4. CFL IMPLEMENTATION ON SHIPBOARD POWER SYSTEM ........................................52
4.1 Hardware in the loop testbed .............................................................................................52
4.2 Fault clearance process in MVDC system.........................................................................56
4.3 CHIL implementation of CFL ...........................................................................................57
4.3.1 Faster CFL implementation ......................................................................................59
4.3.2 CFL response under various fault impedances .........................................................59
4.3.3 CFL response for different system configurations....................................................60
4.3.4 CFL response under different loading conditions.....................................................61
4.3.5 CFL response under different MMC operations.......................................................61
4.4 Summary............................................................................................................................63
5. CONCLUSION AND FUTURE WORK .................................................................................64
5.1 Conclusion .........................................................................................................................64
5.2 Future Work.......................................................................................................................65
5.2.1 Hardware implementation of a ring topology...........................................................65
5.2.2 Validating the system resiliency for cable cut condition..........................................65
5.2.3 System Level Control ...............................................................................................65
5.2.4 Exhaustive noise analysis .........................................................................................65
5.2.5 Integrating multiple CFL units..................................................................................65
5.2.6 Sensitivity analysis of the differential protection scheme ........................................66
References......................................................................................................................................66
Biographical Sketch.......................................................................................................................69
7. vii
LIST OF TABLES
Table 3.1 Executable commands in EtherCAT master configuration……………….. 19
Table 3.2 EtherCAT Frame configuration parameters………………………………. 22
Table 3.3 Parameters defining communication cycle time…………………………... 26
Table 3.4 Parameters defining decision time………………………………………… 29
Table 3.5 Timing of different delays of master……………………………………… 37
Table 4.1 Describing the fault location and the respective disconnect switch
associated with the particular fault location……………………………….
54
Table 4.2 CFL decision time with respect to different system operating conditions…. 62
8. viii
LIST OF FIGURES
Figure 2.1 Basic structure of the CFL system………………………………………… 6
Figure 2.2 2: The steps in the CFL system……………………………………………. 7
Figure 2.3 Kirchoff’s current law……………………………………………………... 9
Figure 2.4 Graphical representation of the percentage differential curve……….…….. 10
Figure 2.5 Describing the flow of current in normal operation and during fault.……... 10
Figure 2.6 Currents flowing through the disconnect switch…………………….……... 11
Figure 2.7 Fault clearance process of MVDC system………………………….………. 12
Figure 3.1 EtherCAT processing “on the fly”………………………………….………. 15
Figure 3.2 Standard EtherCAT frame………………………………………….………. 15
Figure 3.3 Physical Topologies………………………………………………..……...... 17
Figure 3.4 Master-Slave line topology showing direction of data flow………………... 18
Figure 3.5 A TwinCAT view showing the sequential execution of commands and its
respective size………..……………………………………………………...
20
Figure 3.6 The placement of slaves and the number of I/O units connected to each
slave……………………………………………………………………....
21
Figure 3.7 Plot showing the size of EtherCAT frame to the number of slaves………… 23
Figure 3.9 Frame propagation time of the EtherCAT frame………………………..... 25
Figure 3.9 : Number of frames as per the slaves connected in the topology…………. 24
Figure 3.10 Showing the round trip cycle time to the number of slaves in the network... 27
Figure 3.12 Individual timing split-up in the decision time……………………………... 29
Figure 3.13 The two timestamp processing of the RTDS model………………………... 30
Figure 3.14 6 (n+1) cycle times at 50 µs cycle time…………………………………….. 31
Figure 3.15 6 (n+1) cycle times at 100 µs cycle time………………………………….... 32
Figure 3.16 A two cycle time, worst case, EtherCAT response ………………………… 33
Figure 3.17 The time taken by master to compute a fault and generate a trip signal….... 33
Figure 3.18 Events happening in the fault detection by a CFL system for a 50 µs 5
iterations……………………………………………………………….........
34
Figure 3.19 Fault detection time by the CFL for a 50 µs and 3 iterations for each
individual slave in the network…………………….…………......................
35
9. ix
Figure 3.20 Fault detection time by the CFL for a 100 µs and 3 iterations for each
individual slave in the network…….………………………………………..
36
Figure 3.21 Comparison of a round trip cycle time of a line and a ring topology……..… 38
Figure 3.22 Bandwidth relationship between minimum cycle time and number of
slaves………………………………………………………………………...
39
Figure 3.23 The network propagation time with respect to number of slaves…………... 40
Figure 3.24 Random motion of electrons due to increase in temperature………………. 42
Figure 3.25 Additive White Gaussian Noise model……………………………………... 44
Figure 3.26 Depicting the uniform frequency of white noise…………………………….. 45
Figure 3.27 SNR with respect to noise in the signal……………………………………… 46
Figure 3.28 Noise levels………………………………………......................................... 46
Figure 3.29 Node B receiving noisy signal………………………………………............. 47
Figure 3.30 The effect of noise on the current signal…………………………………….. 48
Figure 3.31 Effect of Noise on Slope calculated by the algorithm of the CFL system….. 48
Figure 3.32 Noise in both Node A and Node B…………………………..……………... 49
Figure 3.33 Noise profile in node A and node B………………………………………... 50
Figure 3.34 Effect of Noise on Slope calculated by the algorithm of the CFL system….. 50
Figure 4.1 MVDC shipboard power system with the communication architecture…... 53
Figure 4.2 The location of cable section and disconnect switches as seen in the
RSCAD Model…….………….……………………………………………..
54
Figure 4.3 Selectivity of CFL operation….……………………………………............. 55
Figure 4.4 Execution of the fault clearing sequence………………….……………….. 57
Figure 4.5 Block diagram describing Hardware in the loop (HIL) testing system…… 58
Figure 4.6 HIL testbed………………………………………........................................ 58
Figure 4.7 Showing the fault detection by CFL………………………………………. 59
Figure 4.8 CFL response in different fault impedance conditions……………………. 60
Figure 4.9 CFL response in closed ring and open ring bus system…………………… 60
Figure 4.10 CFL test waveforms under different loading conditions………………… 61
Figure 4.11 CFL detection in various operating modes of MMC's…………………… 62
10. x
LIST OF ABBREVIATIONS
EtherCAT- Ethernet for Control Automation Technology
CFL- Centralized Fault Location
RTE- Real-Time Ethernet
ESC- EtherCAT Slave Controller
WKC- Working Counter
MVDC- Medium Voltage DC
SPS- Ship-board Power System
PDP- Percentage differential protection
AI- Analog Input
DO- Digital Output
XFC- eXtreme Fast Control
XAE- eXtended Automation Engineering
CU- Copper
FO- Fiber Optic
SNR- Signal to noise ratio
AWGN- Additive white Gaussian noise
11. xi
ABSTRACT
The increasing interest and gradual adaptation of a medium voltage direct current (MVDC)
electrical distribution system by the US navy and smart grid designs has demanded a change to the
structure of the traditional electrical distribution system. The development of the power electronics
has led to faster-operating devices and the goal to achieve fault management in time frame of ~ 8
ms demanded a need for an ultrafast fault location and identification system. The traditional
protection system used in alternating current power distribution is well-understood and applied to
a radial distribution system but may lack sufficient response times for a dynamic, intelligent,
looped distribution structure. Hence the centralized fault detection and location (CFL) system is
proposed.
The CFL system, based on ultrafast data communications and processing of sensor data to identify
and determine the location of a fault in the medium voltage direct current (MVDC) shipboard
power system (SPS). This research presents the mathematical models describing the relationship
like the frame size, decision time and the operating time of the CFL system were developed and
verified with the results obtained from an implemented CFL system. The models assess the
performance of the CFL system and assist in estimation of the scaling of the CFL architecture. A
controller-hardware-in-the-loop (CHIL) testbed, interfacing RTDS with an industrial automation
hardware, to demonstrate the methodology and to perform a comprehensive testing and analysis
of a prototype of CFL system.
The results of CHIL experiments demonstrate ultrafast fault detection and precise fault location
operation of the CFL system on a fault current limited MVDC SPS for a line-to-line fault under
different operating conditions of the SPS. Factors affecting the performance and scaling for a
practical CFL implementations were identified and analyzed. The models and analysis in this
thesis are validated by experimental results.
12. 1
CHAPTER 1
INTRODUCTION
1.1 Introduction
ESRDC and U.S. Navy envision a medium-voltage direct current (MVDC) power system to meet
the increasing power requirements on a navy vessel. MVDC power systems are expected to be
advantageous in terms of flexibility and efficiency but have not been widely considered due to
concerns over insufficient fault protection. A centralized fault identification and location (CFL)
system, based on coordinated interaction between the shipboard power system (SPS) and
communication system was developed for an ultra-fast fault identification and location [1]. The
performance models were developed to analysis the CFL system operation and configuration of
the CFL system. This CFL system demonstrated necessary functionality, analyzed based on the
network and physical topology, evaluated for its network performance and tested [2] under various
system configurations on a controller hardware-in-loop (CHIL) cyber-physical testbed in real time.
1.2 Motivation
Traditional relays used in the electric distribution systems cannot meet the highly adaptive
requirements of the new notional breakerless SPS architecture. The development of power
electronic devices provides high operating speed and efficiency. To be on par with these
developments, SPS requires an intelligent and adaptive system to quickly identify and locate a
fault in the power system. To obtain high-speed requirements along with the intelligence and
adaptability, the communication architecture is used as a backbone for the centralized fault
identification and location system (CFL). The CFL system was developed at Center for Advanced
Power Systems (CAPS) [1] and tested on the CHIL testbed [2], [3]. The power system was
modeled and simulated on RTDS and data communication was provided by an industrial
automation hardware. EtherCAT, a network communication protocol, was used for real-time data
acquisition. A systemic approach is followed evaluating the capabilities and performance of the
CFL system and the communication architecture were modeled, tested, verified and presented in
this research.
13. 2
1.3 Literature review
The protective relays are a necessary part of the power system architecture. When a fault occurs
on any part of the system, it should be quickly located and the faulty section needs to be
disconnected. The fundamental requirement of any protective relays are [4]:
1. Selectivity
2. Speed
3. Sensitivity
4. Accuracy
Protective relays have evolved from the electro-mechanical over-current relay to the modern day
microprocessor based relays. The electrical distribution system is divided into two basic protection
zones i.e. primary protection zone and the secondary protection zone. These zones overlap each
other in order to provide redundant system and also to avoid blind areas in the distribution system.
There are many protection schemes designed to perform power system protection. Some of them
are:
1. Overcurrent protection
2. Differential protection.
The overcurrent protection scheme is the simplest and the oldest among the protection schemes.
Overcurrent protection can be classified into two:
Instantaneous overcurrent protection
Instantaneous relays operate without intentional time delays in the system. As the fault
occurs in the system, the logic computes the existence of a fault in the system and sends a
command to the instantaneous overcurrent relays to open. This type of relay is used in
protection from high fault current.
Time-delayed overcurrent protection
In this protection scheme, the operation time of the overcurrent relay is inversely
proportional to the magnitude of fault current. The time-delayed protection scheme
depends on two factors i.e. pickup current and the time delay.
The differential relays operate when the phasor difference between the electrical quantities exceed
the pre-determined value. A current differential relay is based on basic principle of Kirchhoff’s
current law. The basic concept is to sum all the currents in a protection zone. During the normal
14. 3
operation, the sum of currents will be zero but during the faulty condition, the sum of current will
not be zero and hence detects a fault in the system. Differential protection scheme can be applied
to almost all type of faults and hence it is adapted for the fault identification for the MVDC SPS.
A notional breakerless model was proposed for the MVDC SPS architecture. It also emphasizes
the need for an effective fault protection strategy to support the MVDC architecture. The zonal
electric grid architecture for an integrated power system which could be highly survivable and
criteria for fault protection in MVDC system was studied from [5]. The SPS simulation model
which is developed and simulated in RTDS for the study of CFL system was a derivative of the
model proposed in [6]. CFL system, based on an adaptive percentage differential protection
scheme is proposed in [7], [8]. The protection scheme makes decisions by monitoring
instantaneous current values from its various nodes distributed throughout the power system. The
instantaneous current signals are read, digitized and transported in real time through the EtherCAT
protocol developed by [9] and is described and documented in [10], [11], [12]. The cyber-physical
testbed for the testing of the CFL system is shown in [2].
1.4 Outline
This thesis is divided into five chapters. Chapter 2 describes the CFL architecture and details the
algorithm used for fault identification. It also explains the events that generally follow once a fault
is located. Chapter 3 describes the communication system used to achieve ultrafast fault
identification and location. It also provides the mathematical models for reasoning about the
impact of scaling the CFL system and the factors affecting the performance of the CFL system.
Chapter 4 details the CHIL testbed on which the communication and power system architecture
are implemented to perform the Centralized Fault Identification and Location and demonstrates
the implementation of the CFL system on a MVDC SPS. Chapter 5 draws conclusion from the
research and described future work.
15. 4
CHAPTER 2
STRUCTURE OF CENTRALIZED FAULT LOCATION SYSTEM
This chapter discusses the structure of centralized fault location and identification system and the
protection algorithm. The goal is to explore and analyze a faster method of fault location and
identification for the next generation naval ships. For this purpose, CFL system was developed at
CAPS [1] to integrate power system and the communication systems in a highly coordinated
fashion. The MVDC power distribute system may be used to deliver the electrical power in the
next generation naval ships. The CFL leverages digital data acquisition techniques to gather
instantaneous changes in system operation to identify and locate faults in the SPS.
2.1 Protection of MVDC system
The rapid growth in the power electronics led to lower cost and reduction in the size of the power
electronic devices (PED) and the goal to clear the fault in the MVDC system in about 8 ms. Other
advancements to follow were the increase in the performance, efficiency and switching frequencies
of the PED. These, along with the other benefits of using a DC system in terms of power density
and power distribution efficiency, over a conventional AC system led to increased focus in
researching MVDC power system. DC power distribution system is hampered by a lack of
appropriate study in electrical protection strategies. In fact, the protection of DC distribution
systems, especially at the medium voltage level, is recognized to be a notable challenge [5], [6].
The unavailability of DC disconnect switch for the appropriate rating is considered to be a major
factor in the adoption of MVDC for ship power distribution system. In traditional MVAC systems,
fault protection strategies are based on a mechanical switch and occur at zero-current crossing of
the AC wave which occurs at every half cycle. This approach cannot be applied in MVDC systems
because they do not have periodic current zero crossings. The proposed method based on
differential protection can detect and locate fault in DC system and can provide selectivity by
comparing the currents of the two sides of the section which is to be protected is explained in the
sections below.
16. 5
2.2 Basic CFL architecture
A CFL system consists of a master unit and multiple measurements units called slaves. A slave is
a collection of one or more than one analog input cards, digital output cards or combination of
both analog input cards and digital output cards. The master unit is usually located in a remote
location such as a control center and the slaves are distributed at different locations throughout the
power system. The master and the slaves interact over a communication protocol to enable fast
and reliable data communication between each other. The simplified version of a CFL system is
shown in the Figure 2.1 below. The figure, shows a diagrammatic representation of a power
system, with one generator and two loads, on which a CFL scheme is to be implemented. It also
shows the location of the various
In the following power system, as shown in the Figure 2.1, there are multiple disconnect switches
(D), located at multiple location throughout the power system. The disconnect switch is closed
during normal operation of the power system. Once a fault occurs, the function of these disconnect
switch is to open and isolate the respective section of the power system in which the fault has
occurred and hence protect it. The disconnect switch receive instantaneous data measurements to
the analog input (AI) terminals (numbered 1 through 5). The analog input terminals measure the
instantaneous currents, and digitizes the current using an analog to digital (A/D) converter and
transmits the digital signal via the real-time Ethernet (RTE) communication channel to the master.
A fault protection algorithm, which is simultaneously being simulated into the master unit receives
the instantaneous current measurements and executes the protection algorithm, by performing the
necessary calculations, to determine the fault in the power system. Once the fault is identified and
the location is determined by the master, it sends out a control signal, as a response, to the
respective disconnect switches to open and isolate the faulty section from the non-faulty section
of the power system.
2.3 The CFL operation
The operation of the centralized fault location and identification system (CFL) is designed with
the main focus of identification of the presence of a fault in the power system and locating the
specific section where the fault has occurred.
17. 6
Figure 2.1: Basic structure of the CFL system
The CFL system monitors and evaluates the operating condition of all the protection zones of the
power system simultaneously to check for a fault in the normal operating conditions. Once it
detects and locates a fault, it generates a trip signal to initiate the process to isolate the faulty
section and restore stable operating conditions in the system.
The key features which makes the CFL system so important is its operating speed which will be
explained in this section. The Figure 2.2 shows a flowchart explaining the different steps involved
in the operation of the CFL system.
The Master unit is the one which controls and coordinates all the processes in the CFL system.
When the master unit is configured, it establishes communication with all the slaves or
measurement points connected in the master-slave network. The measurement points (M1, M2)
are differential units measuring voltage in the range of (-10 V to +10 V). During the configuration
process of the master, it locates all the slaves physically connected in the master-slave network
and determines the topology (line, ring, star, daisy-chain) in which they are connected to each
other.
Gen.
Load Load
D
D D
D D
Master 1 4 52 3
18. 7
Figure 2.2: The steps in the CFL system
During the configuration process, the master also assigns a specific address to each of the slaves
in order to ensure proper communication between them. This addressing also helps the master to
attain a synchronized operation with its slaves [14]. Once the communication is established
between the master and slaves, the master acquires the data from each of the slaves, it processes
the data by applying it to the algorithm which is simultaneously being run in the master. When the
master determines the algorithm condition to be true, it increments the counter by one which is
initialized at zero. As the counter reaches a threshold value, a trip signal is generated. If the master
determines the algorithm condition to be false, it resets the counter to zero and rechecks the
condition. The reason for setting up of the counter threshold is to improve the reliability of the
algorithm and avoid the false trip in the system. For example, if the counter threshold is set at 1,
sensor noise, switching of generators and loads in the system which might lead to a sudden spike
in the voltage conditions, can result in the generation of a false trip and may lead to the isolation
Master
Condition
check
Counter
Increment
Counter
threshold
Trip
True
slave1slave n
False
EtherCAT Frame
YesNo
Data signal
Logic signal
Reset
counter
19. 8
of a healthy section of the system. Hence, the counter threshold has to be set at a higher value and
hence will evaluate the status of the algorithm for multiple consecutive timestamps instead of one
timestamp.
The operating time of the CFL system depend on factors like:
1. Processing time (𝑇𝑃)
The processing time of the master unit can be assumed in nanoseconds considering
the processing capabilities of the computers these days.
2. Threshold counter (C)
A small counter (1 or 2) threshold can lead to a faster location and detection speed but
can also lead to an unreliable system as it could lead to a false trip. A larger counter
can cause the CFL system to be reliable but can lead to a longer protection time.
3. Sampling time (𝑇𝑆)
Sampling time is the time between two consecutive samples
The equation 1 below shows as
𝑇𝑜𝑝 = 𝑇𝑃 + 𝐶 × 𝑇𝑆 (2.1)
2.4 The CFL algorithm
To meet the high speed and adaptability of the CFL system, the CFL algorithm is based on
percentage differential protection (PDP) algorithm [7], [8] which makes decisions based on
instantaneous values of the current. Differential protection works on the basic principle of
Kirchoff’s current law stating that the currents flowing into a node must be equal to the current
flowing out of the node as can be seen in the Figure 2.3 below.
The percentage restraint characteristic operates on the ratio of operating current to restraint current
in the in the section to be protected. The operating current can be defined as the magnitude of
differential current in the protection zone.
20. 9
Figure 2.3: Kirchoff’s current law
Several different methods have been identified to quantify the amount of restraint current in the
protection zone, which is a measure of the through current in the zone of protection. The restraint
current magnitude will have an impact on the effective sensitivity of a given percentage slope
characteristic and hence to avoid false system response.
The percentage differential protection scheme presented in [7]can be expressed as:
𝐼 𝑜𝑝 = | ∑ 𝐼 𝑛|𝑛
𝑛=2 (2.2)
𝐼𝑟𝑒𝑠𝑡 = ∑ |𝐼 𝑛|𝑛
𝑛=2 (2.3)
| ∑ 𝐼 𝑛|𝑛
𝑛=2 − 𝑆 . ∑ |𝐼 𝑛|𝑛
𝑛=2 ≥ 𝐼𝑚𝑖𝑛 (2.4)
Where,
Irestraint is the restraint current;
Ioperating current is the operate current;
S is slope coefficient;
Imin is the minimum operating current value.
Operating current is the vector sum (keeping in mind the direction of current flow) of all the
currents flowing through the protected zone. Restraint current is the magnitude sum of all the
currents in the particular system. The slope is calculated as the ratio of the operate quantity and
the restraint quantity.
21. 10
Figure 2.4: Graphical representation of the percentage differential curve
The protection calculation for the PDP scheme can be done by calculating the operating current
and the restraint current.
During normal operation, the ratio of the two currents does not exceed the threshold i.e. the slope
lies in the restraint region and hence it's a no-fault condition, therefore, no trip signal is generated.
But, during the fault condition, the slope lies in the operating region which indicated the fault in
the system and hence a trip signal has to be sent to initiate the fault clearance sequence. Figure 2.4
shows the slope of the differential protection scheme.
Figure 2.5: Describing the flow of current in normal operation and during fault
Fault
No Fault
CS- Cable Section
Ioperate
Irestraint
CS
CS
Switch
A
Switch
A
Switch
B
Switch
B
A
B
B
Normal Operation
During Fault
22. 11
During normal operation, the currents flow through disconnect switches and the cable sections as
shown in the Figure 2.5A. When a fault occurs at any point on the cable section, the current
direction changes and all the fault current starts to flow through the fault location to as shown in
Figure 2.5B.
Figure 2.6: Currents flowing through the disconnect switch
Figure 2.6 shows the plot of the currents flowing through the disconnect switches A and B. Before
the fault has occurred, the flow of current can be seen at the point before time 3.5 ms. At time t =
~3.5 ms, the fault occurs and the currents in the two switches now feed into the cable section.
When the CFL system detects the fault in the power system, it sends out a trip signal to the fault
management system to trigger its operations.
The task of clearing short circuit faults in the MVDC systems by DC disconnect switches led to
the development of a new protection strategy for the system: coordinated control operation of the
power converters and mechanical contactors and the fault is clearance by total de-energization of
the affected portion of the MVDC system. Once the power system is de-energized, the system
reconfigures i.e. it isolates the faulty section via DC disconnect switches, and finally re-energizes
the remaining healthy part of the system [15]- [18]. The Figure 2.7 shows the generic voltage and
23. 12
current waveforms of the system during a fault clearing process: fault detection and localization
of the affected section, completely de-energizing of the entire system, isolation of faulted branch
and re-energizing the remaining healthy system.
Figure 2.7: Fault clearance process of MVDC system
The fault clearing process begins with the power converters being forced into current-limiting
mode which will force the fault current to remain at a set limit, identify the fault location by PDP
algorithm via centralized fault identification and location (CFL) system and then shut-down all
sources by bringing the system voltages to zero (i.e.de-energize the system) as soon as the fault
location is identified and open the appropriate disconnect switches to isolate the fault section from
healthy section and finally re-energize the remaining part of the system which is still non-faulty.
The target for the full system response time (SRT), i.e the time taken for the entire fault clearing
process, from fault detection to system re-energization, has been targeted to 8 ms (equivalent to
approximately one-half of a 60 Hz cycle).
Detect and
localize fault
Re-energize
system
De-energize
system
Isolate
faulted
segment
24. 13
Due to the fact that the notional SPS is breakerless, the fault clearance sequence for this MVDC
SPS can be defined as follows [19]:
1. Fault detection and localization – As a fault occurs in any section of the SPS, all power
converters that are connected to the MVDC bus will be forced into current-limiting mode.
This is done by the overcurrent protection feature which is built-in in these converters. The
CFL which is constantly monitoring the system, will work towards detecting and locating
the fault.
2. De-energization of the system – After the fault is detected and the location is identified,
the system will be completely de-energized by bringing the system voltage levels to zero.
3. Isolation of faulty section – Once the system is de-energized, disconnect switches
corresponding to the particular faulty section will be triggered to open once the initial
discharge current from all the capacitance in the MVDC system decays to zero. The
opening of these disconnect switches will isolate the faulty section.
4. Re-energizing the system – After the fault is isolated by opening of the respective
disconnect switches, the converters re-energize the system and hence restart the stable
operation of the entire power system.
2.5 Summary
This chapter discusses the need for protection for the MVDC power system and the basic structure
and operation of the centralized fault location and identification system. This also discusses the
algorithm which makes a decision of the fault in the system.
25. 14
CHAPTER 3
CFL COMMUNICATION SYSTEM
This section discusses the communication architecture and topology of the CFL system. The
section also explains the mathematical modeling of various performance parameters of the CFL
system like the EtherCAT frame size, round trip cycle time of the CFL system and the modeling
of the decision timings of the CFL system. The EtherCAT cycle time model is used to properly
configure the EtherCAT system and the decision time model is used to provide an understanding
of the response time that needs to be satisfied for the CFL system. Factors affecting the
performance of the CFL system like topology, jitter, bandwidth and noise have been listed and
analyzed.
3.1 EtherCAT
EtherCAT (Ethernet for Control Automation Technology) is an industrial automation system and
is widely being adopted as the Real-Time Ethernet (RTE) solutions. The communication efficiency
of EtherCAT makes it suitable for cycle time ≤ 100 µs [9], [13], [20]. The EtherCAT protocol is
optimized for process data and is transported directly within the standard IEEE 802.3 Ethernet
frame. The master is the only node in the EtherCAT segment which is allowed to actively send an
EtherCAT frame and configures, maps the process data on the slave devices; all the input and
output nodes perform frame forwarding towards the next i/o node or slave. The EtherCAT master
sends a telegram that passes through each node. Each EtherCAT slave device uses an EtherCAT
Slave Controller (ESC) which reads and processes the data received by the slave “on the fly”, [14]
and inserts its data in the frame as the frame travels further. When the frame reaches last node in
a segment or branch, it detects an open port and sends the frame back to the master. Figure 3.1
shows the diagrammatic representation of the EtherCAT processing “on the fly”. It shows that
when the frame reaches the slave, it reads the data from the analog inputs and writes the data to
the digital output terminals simultaneously.
27. 16
EtherCAT adds its data into the standard Ethernet frame. Figure 3.2 shows the structure of a basic
EtherCAT frame. Each EtherCAT frame consists of a 2 byte header and may contain one or more
datagrams. The header indicates the type of functionality the master would like to execute i.e.
reading, writing or both read and write. Master configures the number of telegrams in the datagram
corresponding to the number of slaves connected in the topology. Each datagram consists of a 10
byte header. The header is followed by the data payload which represents the payload section in
which the slave reads or writes its data. Finally, the data payload is followed by a 2 byte of working
counter to check for the correct execution of the operation assigned by the master to the datagram
header.
3.2 Hardware
The hardware implementation of EtherCAT devices for the medium voltage DC (MVDC)
shipboard power system (SPS) consists of one master and multiple slaves distributed over the SPS.
EtherCAT master (CX 5140) is an embedded PC from the CX 5100 series based on the Intel®
Atom™ multi-core processors for deterministic Ethernet with real time applications. The master
unit, supplied by a DC voltage of 24 V, is integrated with Microsoft Windows 7 based operating
system consists of a single-core processor operating at 1.46GHz and a non-expandable 2 GB
DDR3 RAM. The slave unit consists of analog input (AI) unit EL 3702, digital output (DO) unit
EL 2262, a coupler or chassis EK 1501 and an Ethernet fiber-optic junction EK 1521. The data
acquisition unit consists of EL 3702 and EL 2262 i.e. the analog input unit and the digital output
unit. EL 3702, based on eXtreme Fast Control (XFC) technology, is a two channel differential
input terminal operating in a voltage range of -10 to +10 V. The EL 3702 block clocks a conversion
time of less than 10 µs, digitizes the voltage to a 16 bit resolution and has a signal oversampling.
The digital output terminal EL 2262, operates on 24V DC voltage, is developed on eXtreme Fast
Control (XFC) technology and supports resistive, Inductive and lamp loads. It is a 2 terminal
digital output terminal with oversampling and can have a 1 µs cycle time. The oversampling factor
is the integer multiple of the cycle time. EK 1521 is a single port fiber optic junction providing
data transfer rate of 100 Mbaud. It enables a conversion from 100BASE-TX to 100BASE-FX.
multimode glass fiber having a thickness of 50/125 micrometer can be used to connect two stations
kept at a maximum distance of 2000 meter with a delay of 1 µs. EtherCAT coupler EK 1501
connects EtherCAT with its terminals using a multimode glass fiber over a distance of 2000 meter.
28. 17
The vendor claims to connect 65,534 terminals to a single coupler unit and achieve data transfer
at 100 Mbaud with a delay of just 1 µs. TwinCAT 3.1 XAE (eXtended Automation Engineering)
is the software supporting the Automation hardware. Integration of TwinCAT in Microsoft Visual
Studio makes it possible to program automation in various languages like C, C++, .NET,
Matlab/Simulink. TwinCAT is divided into various components, for the developmental purposes
of this project we use TwinCAT 3 Engineering.
3.3 Topology
EtherCAT supports multiple physical topologies like line, ring, star and daisy chain as can be seen
in Figure 3.3. An EtherCAT network consists of a master which is connected to multiple slaves.
Figure 3.4 below shows the line topology of an EtherCAT network consisting of one master and
six slaves. A slave unit consists of one or more analog input terminals and digital output terminals.
The sloid arrow shows the direction of data train when it leaves the master and the dashed arrows
show the direction of data train when it reaches the last node.
Figure 3.3: Physical Topologies
29. 18
Figure 3.4: Master-Slave line topology showing direction of data flow
3.4 Modeling of an EtherCAT frame
The EtherCAT master is the only node within the EtherCAT network allowed to actively send an
EtherCAT frame. EtherCAT slave devices use an EtherCAT Slave Controller (ESC) to process
frames “on the fly”. During startup, the master device configures and maps the process data on the
slave devices. The master device can assign each node a configured node address and communicate
with the node via this fixed address. Different amounts of data can be exchanged with each slave,
from one bit to a few bytes. The EtherCAT frame contains one or more datagrams. The datagram
header indicates the type of access the master device has with respect to the particular
node. Execution of an EtherCAT frame may consist of one or more commands. Each of these
commands has an expected working counter value. In other words, the master knows, how many
slave devices are addressed by an individual command and can calculate the expected working
counter. If the master receives a wrong working counter this indicates, that one or more slaves
have a problem [20].
The Figure 3.5 shows the TwinCAT diagnostic view describing the various occurrences of
commands during the execution of a TwinCAT project. In this particular case, only one frame
(Frame0) is sent cyclically during process data communication. The column named cmd in the
Figure 3.5, lists the sequential execution of all the commands used to configure and execute the
Master- Slave network.
Master
CU-FO
converter FO
node
Analog
Input
Digital
Output
FO
node
Analog
Input
Digital
Output
FO
node
Analog
Input
Digital
Output
FO
node
Analog
Input
Digital
Output
FO
node
Analog
Input
Digital
Output
FO
node
Analog
Input
Digital
Output
CU- Copper
FO- Fiber Optic
Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6
30. 19
Table 3.1: Executable commands in EtherCAT master configuration [21]
Table 3.1: Executable commands in EtherCAT master configuration lists and explains all the
commands. The diagnostic also shows the EtherCAT frame size (238 B) and the round trip cycle
time (20.96 µs) for the master-slave network configuration. The round trip cycle time shown in
the TwinCAT scope view comprises of the time taken by the slaves to read the data, conversion
of analog data into digital values that can be written down into EtherCAT frame and the
computation of the algorithm. The computation time of the algorithm can be measured using the
Pentium clock in the master. The master unit essentially a windows machine and can be used to
measure the algorithm computation time by timestamping the start time and the end time of the
Command Abbreviation Name Description Size (B)
1 NOP No Operation Slave ignores command 4
2 ARMW Auto
Increment
Read Multiple
Write
Slave increments address. Slave puts
read data into the EtherCAT datagram
if received address is zero, otherwise
slave writes the data into memory
location.
4
3 LWR Logical
Memory
Write
Slaves writes data to into memory
location if received address matches
with one of the configured FMMU
areas for writing.
4 LRD Logical
Memory Read
Slave puts read data into the EtherCAT
datagram if received address matches
with one of the configured FMMU
areas for reading
5 BRD Broadcast
Read
All slaves put logical OR of data of the
memory area and data of the EtherCAT
datagram into the EtherCAT datagram.
All slaves increment position field.
2
31. 20
algorithm. It takes 530 ns to compute the algorithm for fault identification and location as used in
the present CFL system.
Figure 3.5: A TwinCAT view showing the
sequential execution of commands and its respective size
The Beckhoff master configures all the slave devices connected in the topology and assigns them
an individual address. Master and Slaves communicate over that address. The master calculates
the size of EtherCAT datagram and the size of the entire EtherCAT frame corresponding to the
number of AI and DO channels connected in the topology which will be explained in the later
section.
Cyclic EtherCAT Frame
32. 21
Figure 3.6: The placement of slaves and the number of I/O units connected to each slave
Master generates the number of datagrams equivalent to the number of slaves configured in the
topology i.e. for six slaves connected to a master, the number of datagrams generated will be six.
Each EtherCAT datagram consists of a 10 Byte datagram header, datagram payload and a 2 Byte
working counter. The datagram payload is the numerical sum of the number of fiber-optic
connecter (2 bytes), AI channels (4 bytes) and the DO channels (3 bytes) connected. As per the
present hardware setup as shown in the Figure 3.6, there were 4 slave units each with one fiber-
optic connecter and four analog input and four digital output channels and two slave units each
with one fiber-optic connecter and 2 analog input and digital output channels each, connected in a
line topology. Table 3.2 shows the parameters and their respective size in bytes in creating an
EtherCAT frame.
33. 22
Table 3.2: EtherCAT Frame configuration parameters
Description Abbreviation Size (Byte)
EtherType 𝐸 𝑇𝑦𝑝𝑒 2
Commands 𝐿 𝑐𝑚𝑑 10
EtherCAT Header 𝐸𝑐𝑎𝑡 𝐻 2
Datagram Header 𝐷𝐺 𝐻 10
No. of Slaves 𝑛 𝑠𝑙𝑎𝑣𝑒𝑠 6
No. of Analog Input channel 𝑛 𝐴𝐼 4
No. of Digital Output channel 𝑛 𝐷𝑂 4
No. of Fiber Optic connecter 𝑛 𝐹𝑂 1
Size of Analog Input 𝐿 𝐴𝐼 4
Size of Digital Output 𝐿 𝐷𝑂 3
Size of Fiber Optic connecter 𝐿 𝐹𝑂 2
Datagram working counter 𝐷𝐺 𝑤𝑘𝑐 2
The size of EtherCAT frame (Lframe), number of EtherCAT frames (nframe) payload of a datagram
(DGpl) and size of each individual datagram (LDG) can be calculates by the equations 3.1, 3.2, 3.3,
and 3.4 below:
𝐿 𝐹𝑟𝑎𝑚𝑒 = 𝐸 𝑇𝑦𝑝𝑒 + 𝐿 𝑐𝑚𝑑 + 𝐸𝑐𝑎𝑡 𝐻 + 𝐿 𝐷𝐺 (3.1)
nFrame = ceiling (
LFrame
1500
) (3.2)
𝐿 𝐷𝐺 =∑ (𝐷𝐺 𝐻 + 𝐷𝐺 𝑝𝑙 + 𝐷𝐺 𝑤𝑘𝑐 )𝑛
𝐷𝐺=1 (3.3)
𝐷𝐺 𝑝𝑙 = (𝑛 𝐹𝑂 x 𝐿 𝐹𝑂 + 𝑛 𝐴𝐼 x 𝐿 𝐴𝐼 + 𝑛 𝐷𝑂 x 𝐿 𝐷𝑂 ) (3.4)
34. 23
Figure 3.7: Plot showing the size of EtherCAT frame to the number of slaves
The Figure 3.7 above shows the frame size with respect to the number of slaves connected to the
master. This gives an understanding of the number of bytes of data that can be exchanged with the
number of slaves in the system. As we can see from the Figure 3.7, the x axis shown in the plot
represents the 6 slaves and the y axis represents the size of the frame. As we can compare from the
equation and the number of bytes in the frame match with the TwinCAT scope view shows in
Figure 3.5 and hence can validate the use of the equations 3.1, 3.3, 3.4 to model the EtherCAT
frame size.
Figure 3.8 shows the number of frames that the EtherCAT master needs to generate with respect
to the number of slaves connected to the master- slave topology. The equation 3.2 calculates the
number of EtherCAT frames. The frame number determined by the equation and the number of
frames as can be seen in the TwinCAT scope view in Figure 3.5 match and hence can be used to
35. 24
validate the use of the equation 3.2 to model the number of frames generated by the EtherCAT
slaves.
Figure 3.8: Number of frames as per the slaves connected in the topology
The time taken by the frame (𝑇𝑓𝑟𝑎𝑚𝑒) [22] to send and receive all the bits of data and propagate
through the topology can be represented by the equation 3.5. It is a function of the bandwidth (bw)
of the network and the length of the frame (𝐿 𝑓𝑟𝑎𝑚𝑒).
𝑇𝑓𝑟𝑎𝑚𝑒 =
𝐿 𝑓𝑟𝑎𝑚𝑒 ×8
𝑏𝑤
(3.5)
The Figure 3.9 shows the frame propagation time of the EtherCAT Frame in the network with
respect to the slaves in the system. The EtherCAT hardware used to perform the experiments for
this thesis uses a 100 BASE FX which is a version of fast ethernet over optical fiber and operates
on a bandwidth of 100 Mbps.
36. 25
Figure 3.9: Frame propagation time of the EtherCAT frame
3.5 Modeling of round trip communication cycle time
EtherCAT cycle time can be used to describe the performance index of EtherCAT for an ultrafast
protection system on a real-time Ethernet (RTE)/ EtherCAT network. The minimum round trip
communication cycle time can be denoted as Tc and can be computed as a weighted sum of the
following parameters as shown in Table 3.3: Parameters defining communication cycle timebelow.
The transmission delay of the master [10] can be calculated using the equation below.
𝑇 𝑀
𝑓
= ( 𝑁𝐹 × (𝑆 𝐹𝐻 + 𝑆𝐼𝐹𝐺) + 𝑁 𝑇 × (𝑆 𝑇𝐻 + 𝑆 𝑇)) × 𝑇𝐵) (3.6)
The purpose of the cycle time modeling is to achieve a minimum theoretical cycle time which can
be seen from the equation below.
𝑇𝑐 = 2 × ( 𝑁 𝑇 + 1) × 𝑇𝑝+ 𝑇 𝑀
𝑓
+ (𝑁 𝑇 × 𝑇𝑆
𝑓
) + 𝑇𝑐
𝑝
) (3.7)
37. 26
The Figure 3.10 shows the minimum round trip cycle time with respect to the number of slave
devices connected to the master for a physical line topology.
Table 3.3: Parameters defining communication cycle time
Description Abbreviation
Round trip Cycle Time Tc Formula below
Number of Slaves NT 6
Number of Ethernet Frame NF 1
Number of Frame Header SFH 12 B
Size of Inter-frame gap SIFG 0
Size of the telegram STH 12 B
Number of Ethernet Frame ST 27
Transmission time of one Byte TB 0.028 µs
Maximum delay of Physical Tp 0.5 µs
Master transmission delay TM
f
Formula below
Delay introduced by slave TS
f
0.5 µs
Propagation delay along the cable Tc
P
0.5 µs
As we can see from the Figure 3.10, with six slaves connected in the network, the frame
propagation time is 20.22 µs which is approximately equal to the configured time as can be seen
from the TwinCAT diagnostic in Figure 3.5 hence validates the use of this model for modeling the
cycle time. Figure 3.11 shows the zoomed in graph of the minimum cycle time with respect to the
number of slaves. The Figure 3.10, also gives us an understanding of the cycle time to be
configured in the master according to the number of slaves connected in the topology.
38. 27
Figure 3.10: Showing the round trip cycle time to the number of slaves in the network
As we can see in the Figure 3.5, for the number of slave devices at 15, we achieve a theoretical
cycle time of ~50 µs and hence need to configure a cycle time longer than 50 µs. The equation 3.7
can help in estimating the cycle time of the master- slave system which resemble closely to the
actual cycle time configured by the master and hence can justify the use of equation 3.7 to model
the cycle time of the beckhoff master- slave system.
39. 28
Figure 3.11: Zoomed in on the minimum calculated cycle time from the Figure 3.10
3.6 Decision time modeling
The understanding of the frame size and the round trip cycle time of the master slave network help
us to determine the configuration settings of the automation hardware system and hence the CFL
system in whole. But to understand the decision time of the CFL system it is necessary to
understand the errors and delays added to the systems operation. The decision time of the CFL
system can be divided into three sections i.e. and can be defined as:
1. Time taken by RTDS (TRTDS) to process the signals and its logical operation.
2. Extra time added to the system due to delays and errors (Terror) in the logic processing and
hardware interfacing.
3. The time taken by the Beckhoff (Tbeckhoff) system to read the signals and compute the
algorithm and generate a response signal.
The decision time (Td) is the sum of all the individual timings and can be represented by the
equation below.
Td = TRTDS + Terror + Tbeckhoff (3.8)
TRTDS = nprocessor x TRct (3.9)
Tbeckhoff = (niter + 1) x Tct (3.10)
40. 29
T
error
= T
hsr
+ T
bpr (3.11)
The Table 3.4 shows the description of each of the terms mentioned in the equations above. The
following sections will explain each of the three split up as described above. The Figure 3.12:
Individual timing split-up in the decision time shows the individual timestamps of the processes
involved in the decision time of CFL.
Figure 3.12: Individual timing split-up in the decision time
Table 3.4: Parameters defining decision time
Td Decision time
TRTDS RTDS simulation time
Terror Time due to errors
Tbeckhoff Beckhoff cycle time
nproc step RTDS processing step
TRct RTDS cycle time
niter Number of iteration
TBct Beckhoff cycle time
Thsr Hardware sync error (RTDS & Beckhoff)
Tbpr Beckhoff processing error
41. 30
3.6.1 RTDS processing
The ship power system model is simulated in RTDS at a time step of 50 µs. The fault is initiated
in RTDS as can be seen by a blue curve in the Figure 3.13. After the fault is initialized, it computes
a logic which enables the analog signals to be sent out of the RTDS. This RTDS logic is processed
onto two different controls processer and accounts for two timestamp processing time. The signals
are sent out from the front panel analog output and in the range of (-5 V to +5 V). The Figure 3.13
shows the two timestamp process, (50 µs each) required to process and send the signal out from
the RTDS.
Figure 3.13: The two timestamp processing of the RTDS model
tRTDS = nprocessor x tRct (3.12)
The equation shows the number of processing steps taken multiplied by the simulation time of
each step determines the time taken by RTDS to compute the logic and send the output.
100 µs
42. 31
3.6.2 Beckhoff processing
The front panel analog input from RTDS sends the signal to the Beckhoff analog input terminals
which reads the analog signal. These analog signals are converted to digital signals by an A/D
converter and subsequently uploaded onto the data train eventually arriving at the master. The
master reads the data train and extracts values from the slaves. This extracted information is used
to process the protection algorithm. The counter threshold for the protection algorithm is set to
five, the algorithm computes for five consecutive iteration to determine a fault in the SPS. The
master reads the data when the first data train arrives at the analog input terminal and sends out
the decision it makes from the first dataset in the second data train, resulting in n+1 cycles (where
n is the number of iterations). The cycle time of the master can be configured from 50 µs and
above.
Figure 3.14: 6 (n+1) cycle times at 50 µs cycle time
43. 32
Figure 3.15: 6 (n+1) cycle times at 100 µs cycle time
tbeckhoff = (niter + 1) x tct (3.13)
The equation above computes the time taken by the master to determine the fault. Substituting tct
as 50 µs and niter as 5, the time taken by the master to compute the algorithm and send out the
response is 300 µs as can be seen from the Figure 3.14 and for the cycle time of 100 µs for a 5
iteration process, the master takes 600 µs to respond to a fault as shown in Figure 3.15. Figure
3.14 and Figure 3.15 above shows an oscilloscope plot of the n+1 cycles.
3.6.3 Hardware synchronization
A master-slave network has various components distributed throughout the topology and it is
useful to make them operate in synchronization with each other. At times closely linked to each
other. The slave units are governed by local clock embedded in the EtherCAT slave controller
44. 33
(ESC). The distributed clock (DC) [21] concept of the EtherCAT is used to synchronize the local
clocks. The master is assigned with the task to synchronize the DC at less than 100 ns system
accuracy irrespective of the distances between the individual controller and the network topology.
Figure 3.16: A two cycle time, worst case, EtherCAT response [21]
Figure 3.17: The time taken by master to compute a fault and generate a trip signal
Worst
45. 34
There is another synchronization error between interfacing of the RTDS and the slaves. The slaves
and RTDS are not synchronized by means of an external clock. Due to the phase shift in the local
clocks of each controller, there may be a single timestamp error.
The Figure 3.17 shows the time taken by RTDS to simulate the fault in the SPS model and the
time taken by the beckhoff to compute the fault and give a response. The 450 µs duration between
the initiation of the fault and the response from the master as shown in the figure consists of the
RTDS processing time, hardware synchronization error and the beckhoff processing time.
In the Figure 3.18 shows the timing of each of the events happening in the complete CFL
process.
Figure 3.18: Events happening in the fault detection by a CFL system for a 50 µs 5 iterations
As we can see in the Figure 3.18 the time taken by the CFL to respond to a fault in a SPS consists
of three sections i.e. the time taken by RTDS, time taken by beckhoff system and the hardware
synchronization error. The blue curve shows the initiation of fault in RTDS which takes 100 us to
simulate the logic and send out the current signal from its front panel analog output terminals
(shown in green) to the analog input terminals of the slaves. There is no synchronization between
the simulation tool and the controller hardware and hence there may exist a 1 time step delay. The
46. 35
beckhoff delay of 2 time step will cause another 100 us delay in read of signals by the analg input
of the slaves. The slaves read and send the data to the master for processing in the algorithm and
this is don for 5 consecutive iterations and hence take 300 us to generate a response signal as shown
in the red. This decision of the beckhoff system is sent back to RTDS again and which triggers
some further simulation and finally generates a signal which triggers the fault clearing sequence
to operate.
Figure 3.19: Fault detection time by CFL for a
50 µs and 3 iterations for each individual slave in the network
The Figure 3.19 and Figure 3.20 above shows the fault detection time when each slave is added to
the master- slave topology. The underlying assumption in testing above is that the last slave unit
is connected to the fault location. Figure 3.19 shows the CFL detection time for a 50 µs EtherCAT
cycle time and 3 iterations.
Figure 3.20 shows the CFL detection time for a 100 µs EtherCAT cycle time and 3 iterations. As
we can see, there is a one cycle or two cycle time latency in the CFL detection.
47. 36
Figure 3.20: Fault detection time by CFL for a
100 µs and 3 iterations for each individual slave in the network
3.7 Factors affecting performance of CFL
In order to fully understand the capabilities of the CFL system, understanding of the parameters
affecting the response of CFL is very critical. The few parameters which can affect the system
response are as follows:
3.7.1 Topology
This is one of the indices which could affect the performance of the CFL system. The network
which master and slaves connects can affect the achievable cycle time of the system. This section
discusses about the two topologies, line topology and ring topology.
The equations listed below can be used to calculate the communication cycle time. Where Tcycle
represents the communication cycle time, Tframe represents the time taken by the frame to propagate
through the network. Tnetwork consists of the forwarding delays produced by the slave devices and
the delays caused by physical layer components [22].
Tcycle = Tframe + Tnetwork (3.14)
48. 37
The factors determining the length of frame has been discussed in the previous section. The time
for frame propagation also depends on the bandwidth (bw) and can be shown in the equation
below.
Tframe = Lframe x 8 / bw (3.15)
1. Line topology
Line topology is the simplest network topology and also one of the most widely used. This
topology avoids creation of a complex mesh of cables and leads to easy maintenance of the system.
The equations below show the calculations for the network propagation time and the forwarding
time by each node. These timings combined with the frame propagation time accounts for the total
communication cycle time.
Tnetwork = Tcable + Tmaster + (n-1) x Tnode + tEndNode (3.16)
Tnode = tMMp + tMMf + 2 (tRx + tTx) (3.17)
As the frame propagates through the slaves it reaches the last slave and the master detects an open
node. The last slave will send the frame straight back to the master and can be computed by the
equation below.
TEndNode = tMMP + tRx + tTx (3.18)
Table 3.5: Timing of different delays of master
Symbol Description Value (ns)
tMMf Forwarding delay 265
tMMP Processing delay 305
tRx Receive delay 320
tTx Transmit delay 140
2. Ring topology
Ring topology provides an advantage over the line topology by creating a return path for the data
train to return to the master. The last slave will have a return path to forward the data from the last
slave back to the master. This return path can also lead to a redundant topology as there is an
additional path for the data to flow once a section of the cable is lost.
49. 38
Tnetwork = Tcable + Tmaster + ∑ Tnode (3.19)
Tnode = tMMp + tMMf + 2 (tRx + tTx) (3.20)
The Figure 3.21 shows the comparison of round trip cycle time of a line and ring topology. The
line and ring topology can have comparable performance for a small network but ring topology
has greater performance for a large network.
Figure 3.21: Comparison of a round trip cycle time of a line and a ring topology
3.7.2 Jitter
Jitter is the short-term variation of the times of the respective bits from their ideal times [26] In
short jitter can be described as latencies in the network stations which result in the variation of the
cycle time [23]. The equation below can be used to calculate the jitter occurring in the system.
Jitter can be caused in the master-slave network if the master is not configured for a proper cycle
time. If the master cycle time is lesser than the total communication cycle time, jitter may occur..
50. 39
A large jitter in the network can cause the CFL system to miss a cycle of data collection and can
cause delays in the fault identification and location.
J =|Tc − Tcm| / Tc (3.21)
Where,
Tc is the nominal cycle time configured at the beginning of the network
Tcm is the actual measured network time
Figure 3.22: Bandwidth relationship between minimum cycle time and number of slaves
3.7.3 Bandwidth
Bandwidth can be defined as the amount of data that can be transmitted in a fixed amount of time.
In the equation below [23], MCT represents the minimum pooling period of the slave devices. For
an EtherCAT system, the MCT is calculated to be 17.28 µs. For a 100 Mbps transmission speed,
non-real-time bandwidth (NRB) can be computed from the equation 3.22 below.
NRB =
|Tc − MCT|
𝑇𝑐
× 100 (3.22)
51. 40
Figure 3.22 shows the bandwidth relationship between minimum cycle time to the number of
slaves connected in the master-slave topology [22]. This relationship is developed for a fast
Ethernet of 100 Mbps and Gigabit Ethernet of 1 Gbps for a 4 byte data. As we can see, the gigabit
Ethernet performs better than the fast Ethernet and can achieve faster round trip cycle time. The
analysis of the effect of bandwidth on the round trip cycle time of the system can help in better
selection of the parameter of the CFL system for an actual ship.
Figure 3.23: The network propagation time with respect to number of slaves
3.7.4 Network propagation time
The time taken by the frame to propagate throughout the network depends on factors like payload
size of the data, the length of the cable section and the number of nodes connected in the network.
For a transmission speed of 100 Mbps and a constant payload size of 4 bytes, the network
propagation time with respect to the number of slaves connected in the topology can be shown in
the Figure 3.23.
52. 41
3.7.5 Noise
The CFL system relies on reliable data communication for performing its fault location and
identification function. Noise can be a critical factor causing a disturbance in the communication
channel and could possibly lead to an incorrect CFL fault detection. Noise is a relative concept
and can mean differently for different conditions, hence, defining noise is important.
Noise can be defined as a random, undesirable energy that enters the communication system via
the communicating medium and interferes with the transmitted message [27], [28].
A preliminary analysis of effects of noise on the CFL system was performed. The aim of this study
was to explore on the question: At what amount of noise in the measurements will the CFL system
generate a false decision.
3.7.5.1 Sources of noise in a system
Noise in the system can arise due to many internal and external factors and it is practically
unavoidable. The noise can cause degradation in the performance of both analog and digital
systems in which the receiver receives an adulterated version of the data sent to it by the sender
and hence it is unable perform its required functionality thereby reducing the efficiency of
communication system.
Sources of noise can be classified into two
1. Internal noise
2. External noise
1. Internal noise
Internal noise is caused by the disturbances in the internal electric due to design imperfections or
random motion of the electrons. Some examples of internal noise are listed below:
THERMAL NOISE (JOHNSON NOISE)
Thermal noise or Johnson-Nyquist noise is an electronic noise generated by the thermal agitation
of the electrons flowing inside the electrical conductors. Thermal noise is generated by all devices
which cause resistances to the flow of electrons. As the temperature increases, the kinetic energy
in the conductor increases which increases the random motion increases which increases the
thermal noise can be seen in the Figure 3.24.
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Figure 3.24: Random motion of electrons due to increase in temperature
Results of experiments performed by Johnson stated that the power of noise measured in a
conductor is directly proportional to the absolute temperature and bandwidth of the measuring
instrument. This was theoretically studies by Nyquist which resulted in the formulation of the
mean square noise voltage which can be defined as shown in the equation (3.23).
V2
= 4kTBR (3.23)
Where,
k is the Boltzmann’s constant,
T is the absolute Temperature,
B is the bandwidth of noise,
R is the resistance offered by the conductor.
SHOT NOISE
Shot noise is used to describe the type of noise which arise from the random fluctuations in the
emission of electrons from cathodes in vacuum tubes. Shot noise, occurs due to the ejection of
charge career, in semiconductors that have a considerable amount of charge in the pn junction.
This charge creates a current which is effectively a summation of current pulses. The equation 3.24
shows the current generated due to shot noise as a series of current pulses.
i(t) = Io + in(t) (3.24)
Where
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𝑖(𝑡)- total current (A)
0I - constant current (A)
𝑛(𝑡)- noise current (A)
2. External noise
External noise is caused by factors external to the system like lightning, switching of electrical
equipment, signal interference and may also be caused due to faults in the system. Below is the
list of some external sources of noise.
Electrostatic interference
Electromagnetic interference
Radio frequency interference
The devices which lead to sudden changes in the voltage or current levels are sources of noise. It
is also called as impulse noise. Some of the common sources of impulse noise are listed below
[29], [30]:
Switching of large electrical devices
Lightning strikes
Electrical Faults
High power equipment.
The mitigation of noise is essential for the CFL system as an improper signal could cause the
system to detect false trip and might lead to the isolation of a healthy section of the power system.
The following techniques can be applied to reduce the effects of noise.
Physical isolation of noise generating equipment from noise-sensitive equipment
Electrical isolation
Shielding or screening of noise sources and equipment affected by noise
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Figure 3.25: Additive White Gaussian Noise model
3.7.5.2 Additive White Gaussian noise
Additive white Gaussian noise is one of the most widely used models to represent a random
process. For modeling purposes, it is fair to assume the noise in the communication systems to be
Additive White Gaussian Noise (AWGN) [27], [28].
Additive
Noise can be assumed to be additive because the noise signal is usually added to the information
bearing clean signal. The Figure 3.25 shows the representation of a noise model. In this, the clean
signal is added with a noise and hence the receiver receives the signal with additive noise.
White
White noise is assumed to be a random signal with a constant power spectral density, given that
the noise is not band limited by some filter bandwidth.
Power spectral density of a white noise can by expressed as fpo can be seen in the Figure 3.26.
White noise = fpo = Constant
Gaussian
We generally term noise as a random power and hence it can also be assumed to have voltage
amplitudes following a Gaussian distribution.
56. 45
Figure 3.26: Depicting the uniform frequency of white noise
3.7.5.3 Signal to Noise ratio (SNR)
The ratio of signal voltage to noise voltage read by the receiver can be used to determine the
strength of the signal. The SNR model can be used to determine how well the communication
system will operate. In communication systems, generally, the signal voltage at the source remains
stable. The noise is added to the signal voltage during its propagation in the cable can depend on
the length of the cable and the cable resistance. The equation 3.25 can be used to calculate the
SNR.
SNR= 20 × log10(
𝑉𝑠𝑖𝑔𝑛𝑎𝑙
𝑉𝑛𝑜𝑖𝑠𝑒
) (3.25)
The SNR is usually expressed in decibels (dB), it is defined as the logarithmic ratio of the signal
voltage (Vsignal) and noise voltage (Vnoise).
The Figure 3.27 shows a relation between the SNR and noise percentage in a signal. It can be seen
that the higher the SNR, the lower the noise percentage and hence easier to provide acceptable
performance.
Figure 3.28 shows the noise levels which are added to the signal when the SNR is 10 dB, 15 dB
and 20 dB, the blue curve representing SNR of 10 dB shows a higher variation in the signal levels
when compared to the SNR of 15 dB or 20 dB. This can also lead to an understanding that the
higher signal to noise ratio provides a better chance for a cleaner signal.
Noise
Frequency
Constant
57. 46
Figure 3.27: SNR with respect to noise in the signal
Figure 3.28: Noise levels
3.7.5.4 Noise modeling on CFL system
The CFL system is based on instantaneous data measurements from analog input terminals
distributed throughout the power system. Using the AWGN model and SNR model, it is possible
58. 47
to mimic the effect of noise that is possible to be observed on the fault identification process. To
model the noise in the CFL system, two cases were studied. In case 1, only one of the two analog
input nodes receive a noise and the second receives a clean signal. In case 2, both the nodes of the
analog inputs receive noise signal. This study has an underlying assumption that 2 analog input
nodes are being monitored for a line-to-line fault in the SPS model described in the previous
chapters.
CASE 1: Only one node receives noise
In Figure 3.29, there are two nodes i.e. “Node A” and “Node B”. In this case we assume having
noise only in one of the two nodes (Node B). Hence the “Node B” receives a clean signal with an
additive noise signal. The current signal is generated by RTDS for a line-to-line fault in the SPS
simulation model and the noise signal with the particular SNR is being modeled in Matlab.
Figure 3.29: Node B receiving noisy signal
Figure 3.30 shows the effect of noise on the current signal. The figure represents the condition
when a fault has occurred in the SPS. The blue curve represents a clean signal which is being
generated by RTDS. The other curves represent a noise added to the clean signal. As can be seen
from the Figure 3.30, the SNR of 10 dB has a higher amplitude of variation compared to the others
which also validates the statement that the signal with higher value of SNR can be read better by
a receiver.
59. 48
Figure 3.30: The effect of noise on the current signal
Figure 3.31: Effect of Noise on Slope calculated by the algorithm of the CFL system
Figure 3.31 shows the effect of noise on the slope calculation of PDP algorithm which determines
the fault in the SPS. The slope value to determine a fault in the system is assumed to be 0.4. The
60. 49
curve representing SNR 10 dB represent a noise level of approximately 30%. As we can see, the
fault occurs at time 8 µs and at 9 µs the slope value crosses the threshold of 0.4, but due to noise
in the signal, the slope appears to be ~0 leading to a faulty decision. Also at time 5 µs and 6 µs,
the clean signal reads ~0 but the amplitude of the noise is ~0.4. This could possibly lead to a faulty
operation of CFL. This is also a factor to be considered when setting the slope and the counter
threshold for the CFL system.
CASE 2: Noise in both the nodes
In Figure 3.32, there are two nodes i.e. “Node A” and “Node B”, in this case we assume both the
nodes (Node A and Node B) receive noisy signal. The current signal is being generated by RTDS
for a line to line fault in the SPS simulation model and SNR model is used to add the noise to the
clean signal in Matlab.
Figure 3.32: Noise in both Node A and Node B
Figure 3.33 shows the noise profile for the two nodes (Node A and Node B) for SNR of 10 dB, 15
dB, and 20 dB.
Figure 3.34 below shows the effect of noise on the slope calculation by PDP algorithm for the
CFL system. The slope threshold is set at 0.4. We can see for SNR of 10 dB and 15 dB, the
magnitude of variation caused by the noise, for some instances, is greater than 0.4 and could
possibly lead to a false detection or no detection by the CFL system.
61. 50
Figure 3.33: Noise profile in node A and node B
We can see from the curve of SNR 10 dB, the slope crosses the threshold of 0.4 for two consecutive
iterations on two occasions. This will lead to a faulty counter increment but ay not lead to a faulty
CFL detection. The fact that this event occurs twice with an interval of one timestep indicates a
possibility of false detection by CFL system. This analysis raises the question on the amount of
filtering needed to prevent this occurrence and also on indicates a deeper analysis on the slope
threshold value and the counter threshold value.
Figure 3.34: Effect of Noise on Slope calculated by the algorithm of the CFL system
62. 51
3.8 Summary
This chapter describes the various models used to predict the CFL system performance. These
performance models like round trip cycle time, frame size, decision time can also be used to
understand the CFL system scaling for a full ship system. Various factors affecting the CFL
performance like topology, jitter, bandwidth, noise were identified and were studied.
63. 52
CHAPTER 4
CFL IMPLEMENTATION ON SHIPBOARD POWER SYSTEM
This chapter presents the hardware implementation of the CFL system on a Beckhoff automation
hardware with EtherCAT as a network protocol for data communication. The CFL system was
implemented and demonstrated on a hardware in the loop (HIL) simulation on RTDS and tested
for various fault impedance and system operation conditions.
4.1 Hardware in the loop testbed
The CFL system follows a master-slave line topology communicating over a deterministic real-
time Ethernet (EtherCAT). The Figure 4.1 shows the 1 MW, 5 kV MVDC SPS, along with the
master-slave serial topology, modeled for the study. There are two AC generators each rated at 1
MW. Each generator is interfaced to the 5 kV MVDC bus through a 1 MW MMC. An average
value model of the MMC which has been derived from experimental results of CHIL
implementation of MMC has been used. Each MMC is current limited to 228 A (rated operation,
1 MW, 200 A at 5 kV). There are 12 cable sections in this model. The impedances and lengths of
the cable sections are presented in [3] MMC 1 and MMC 3 are source MMCs to which the 1 MW
generators are interfaced. There are two loads on the system, each rated at 500 kW on the 5 kV
DC bus. The MMC's can be operated in voltage source mode (VSM) or current source mode
(CSM). The 5 kV DC bus ring bus has dc disconnects at each end of the cable section so as to
maintain stable operation of the system in an occurrence of a fault by rerouting the power generated
to the load centers. The MVDC ship power system model is implemented on a real time digital
simulator (RTDS) operating at a 50 µs time step and interfaced with an industrial automation
hardware on which the protection scheme is implemented. The communication protocol between
master and its various slaves is EtherCAT.
The 1 MW MVDC SPS is simulated in RTDS, it consists of a centrally located master along with
slaves distributed throughout the MVDC SPS. The slaves consist of a fiber-optic converter, which
converts 100 base TX to 100 base FX, along with multiple analog input channel and digital output
channel connected to the fiber-optic connector for read and write of data to and from the simulation
model. This HIL simulation model [2] consists of has nine analog input channels gathering
64. 53
instantaneous current values from the disconnect switches located across each cable section
throughout the SPS and nine digital output terminals sending the status signal out to indicate the
fault location and also to trigger the fault clearing sequence. The analog and the digital terminals
communicate with the master over EtherCAT and the data packet is transmitted over fiber optic
cables between each slave.
Figure 4.1: MVDC shipboard power system with the communication architecture
The location of protection zones on the SPS are designated in an overlapping manner such that
they provide redundant protection to each of the cable sections of the SPS and at the same time do
not create a false trip signal to open the disconnect switches in the adjacent cable. The Figure 4.2
is a screenshot of the RSCAD runtime from the SPS model. There are five cable sections on which
line-to-line fault can be applied. The Table 4.1 shows the fault location and the respective
disconnect switch which needs to open in order to isolate the faulty cable section.
Figure: MVDC shipboard Power system with the communication architecture
CS1 CS2 CS3
CS4
CS5CS6CS7
CS8
F I O
FIO
F
IO
F I O
F
I
O
Master
F
I
O
MMC 4
Input signals (Current) from RTDS to Beckhoff Analog Input
Output signal from Beckhoff Digital Output to RTDS GTDI
Master Slave Connection (Fiber)
Disconnect Switch
F- Fiber optic converter junction
CS- Cable Section
I- Analog Input Terminal
O- Digital Output Terminal
F
I
O
Slave
UnitMMC 3 MMC 2
MMC 1PGM
PGM
Load
Load
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Figure 4.2: The location of cable section and disconnect switches
as seen in the RSCAD Model
Table 4.1: Fault location and the respective disconnect switch
associated with the particular fault location
Fault Disconnect Switch
Cable 1 A B -
Cable 2 B J C
Cable 3 C Q D
Cable 4 D L F
Cable 5 F N A
Cable 1
Cable 2
Cable 3
Cable 4Cable 5
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As we can see from the Table 4.1, if there is a fault in cable 1, disconnect switches A and B need
to open. But disconnect switch A is also associated with a fault in cable 5 and disconnect switch
B is associated with the fault in cable 2. The CFL system needs to ensure that it only sends
commands to isolate the fault in cable 1 and do not affect the healthy sections of the remaining
power system.
The Figure 4.3 shows the plots of faults in each cable sections. As it can be seen from the plots
below, the disconnect switches guarding the respective cable sections open and cause the trip
signal to initiate the fault clearing sequence.
Cable Fault 1
Cable Fault 3
Cable Fault 2
Cable Fault 4
Figure 4.3: Selectivity of CFL operation
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4.2 Fault clearance process of MVDC system
The fault clearing in the breakerless MVDC system can be achieved by the total de-energization
of the affected section of the MVDC shipboard power system leading to isolation of the affected
section via the opening operation of the disconnect switches while the system is de-energized and
finally re-energization of the remaining section of the shipboard power system.
The Figure 4.4 shows the sequential execution of the fault clearing sequence.
As the fault may happen in any part of the SPS (e), the fault current rises (a, b), the power
converters feeding the ring bus will be forced into current limiting mode by their built-in
overcurrent protection scheme. It then leads to a complete de-energization of the system by
ramping the system voltage to zero as shown in (c, d). The CFL system detects and locates the
fault (f) and initiates the fault clearing sequence. The fault clearing sequence isolates the faulty
section from the healthy section and commands the opening of the disconnect switch. Once the
faulty section is isolated, a control signal (g) indicating the clearance of the fault will be sent to
the converters to initiate the system recovery. The system recovers by raising up the voltages (c,
d) for zero to operating conditions. Hence completes the recovery of the MVDC system.
4.3 CHIL implementation of CFL
To analyze the performance of the CFL scheme, a HIL simulation model was developed as
described in the section above i.e. a 1 MW, 5 kV model with two generating units represented by
MMC’s capable of operating in VSM and/or CSM and two loads connected to the DC ring bus
configuration.
Cable Fault 5
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Figure 4.4: Execution of the fault clearing sequence
The Figure 4.5 shows a block diagrammatic representation of the various sections of the CHIL
testbed and Figure 4.6 shows a photograph of the actual CHIL test bed with the CFL system and
the RTDS at CAPS. The CFL hardware setup consists of one master unit interacting with six slave
units over EtherCAT. The testbed is a scaled down representation of the anticipated full-scale
MVDC shipboard power system. The various tests and the simulation results performed on the
CHIL setup are described in the sub-sections below [2].
69. 58
Figure 4.5: Block diagram describing Hardware in the loop (HIL) testing system
Figure 4.6: HIL testbed
70. 59
4.3.1 Faster CFL implementation
To validate and evaluate the implementation of CFL scheme on the new hardware setup a CHIL
test-bed was created as shown in the block diagram in Figure 4.7. The core motive behind this test
was to test the fault identification and location timings and to compare them with the previously
used hardware. The RTDS simulates the SPS model at a 50 µs time step while the round trip cycle
time of CFL hardware is 50 µs. A bolted rail to rail fault was tested at various location on the DC
ring bus. The time taken by the new CFL hardware to identify the fault in the system is 800 µs, as
shown in Figure 4.7, which is nearly four times faster than the fault identification time in the
previously used hardware.
Figure 4.7: Showing the fault detection by CFL
4.3.2 CFL response under various fault impedances
This section describes the response of CFL scheme for various fault impedances. During a high
impedance fault, the fault current is relatively low and it may become difficult to distinguish
between load currents and fault currents. But CFL, which operates on PDP scheme, is able to
perform its fault location and identification job even in this fault condition. The Figure 4.8 below
shows the CFL response under low impedance (fault impedance 0.1 Ω) fault and high impedance
(fault impedance 20 Ω) fault conditions. As we observe, the fault detection time in either of the
fault impedance conditions was similar and hence we can validate the CFL operation under various
fault impedance conditions.
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Figure 4.8: CFL response in different fault impedance conditions
4.3.3 CFL response for different system configurations
The CFL scheme was tested to determine if a fault can be identified in the system irrespective of
whether the SPS is run in radial or ring bus configuration. Figure 4.9 shows the CFL fault detection
under the closed ring and open ring SPS configuration. As we can see, the CFL system is able to
detect the fault in the system in the event of a fault in the open ring configuration of the SPS. Hence
validates the CFL operation.
Figure 4.9: CFL response in closed ring and open ring bus system
72. 61
4.3.4 CFL response for different loading conditions
This section aims to verify the operation of CFL under different loading conditions. The higher
loading condition may lead to the slower rise in the magnitude of the fault current which might
cause inaccurate operation of CFL system. The SPS was loaded differently in the two test cases
that in case one the generators were producing 0.544 MW and in the case two the generators were
producing 0.125 MW. As we can see in Figure 4.10, the CFL scheme demonstrates the fault
detection in both the system loading condition.
Figure 4.10: CFL test waveforms under different loading conditions
4.3.4 CFL response under mmc VSM and CSM operation
To observe the CFL response under various MMC operating configuration, two cases were created.
In the first case, both the MMC's were made to operate in VSM whereas in the second case, MMC1
was operating in VSM and MMC 3 was operating in CSM. Figure 4.11 shows the fault detection
time by CFL in both the conditions when both the MMC’s i.e. MMC1 and MMC 3 are being
operated in VSM and the curve in green represent the CFL detection time when MMC1 is being
operated in VSM and MMC 3 is being operated in CSM. Figure 4.11 it is shown that the CFL
operates with satisfactory performance under different system configurations.
73. 62
Figure 4.11: CFL detection in various operating modes of MMC's
r system.
Table 4.2: CFL decision time with respect to the different system operating conditionslists all the
above experiments to check and validate the operation of the CFL system in different SPS
configurations. As we can see, the CFL system is able to operate in a fast and precise manner. This
table also shows the comparison of the older CFL system with the new CFL system and shows
that the new system is ~4 times faster than the older system.
Table 4.2: CFL decision time with respect to the different system operating conditions
CONDITION TYPE TIME (µs)
FASTER IMPLEMENTATION NEW SYSTEM 800
OLDER SYSTEM 4 ms
FAULT IMPEDANCE LOW IMPEDANCE FAULT 750
HIGH IMPEDANCE FAULT 800
POWER SYSTEM
CONFIGURATION
OPEN RING 750
CLOSED RING 800
LOADING CONDITION 0.544 MW 750
0.125 MW 800
OPERATING MODES VSM- CSM 750
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VSM- VSM 800
4.4 Summary
This chapter provides an overview of the CHIL testbed used to demonstrate the ultrafast CFL
system operation. The new system is more than 4 times faster than the older CFL system. The
CFL system was tested for different system operating conditions and the whole fault clearing
process is described.
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CHAPTER 5
CONCLUSION AND FUTURE WORK
5.1 Conclusion
A system which is ultrafast and precise in fault detection and location called centralized fault
location and identification (CFL) is seen to perform its necessary functionality. The factors aiding
to assess the scaling and the performance of the CFL system were identified and analyzed for a
line-to-line fault in the medium voltage DC shipboard power system. This research presents a
demonstration of a faster CFL system and the analysis of the performance models of the centralized
fault identification and location (CFL) system for a MVDC shipboard power system.
Two types of CFL topology were discussed and were tested for the fault current limited MVDC
power system. The performance models demonstrate a methodology to configure the CFL system
and to scale the prototype system for a real world operation. The key feature of the research can
be summarized as follows:
1. Mathematical models to understand the performance of the CFL system were designed
and validated with experimental results.
2. Models were used to understand scaling of the prototype CFL system for an actual
shipboard power system.
3. The fault identification system was implemented on a new, industrial automation
system hardware platform based on data acquisition and was tested on a CHIL testbed
to detect and locate fault in the SPS.
4. The CFL system is intelligent and ultrafast in fault detection and precise in fault
location.
5. The performance models indicate the number of slaves as a major factor affecting the
design of the CFL system.
6. Two type of physical topology were studied and its effects on CFL system were
analyzed. It is found that the ring topology could have multiple possible benefits than
using a line topology.
76. 65
7. The CFL system was tested of various configurations of the SPS and was found to
accurately and rapidly detect the line-to-line fault in the cable section in around 300 µs.
5.2 Future Work
5.2.1 Hardware Implementation of a ring topology
Line topology can provide with the basic functionality of fault location and identification
but faster response time can be achieved with a ring topology. Using ring topology can provide
additional benefits like faster cycle time, resiliency in loss of one communication cable.
5.2.2 Validating the system resiliency for cable cut condition
Due to some reasons, there can arouse a condition where a cable is cut in the system.
Testing of system response and maintaining the CFL functionality is an important task under such
conditions.
5.2.3 System level control
CFL system as described in the chapters above, provides a standard functionality of fault
location and identification for a MVDC power system. After the fault has been detected, a system
level control has to take over the responsibility of system recovery
5.2.4 Exhaustive Noise analysis
Noise is a major source of disturbance and can lead to faulty operation and loss of
sensitivity of the CFL system. A detailed noise analysis using various noise models and
determining the appropriate noise level which this system can withstand can provide better
understanding of the system performance.
5.2.5 Integrating multiple CFL units
The CFL system was tested for a 1 MW model of MVDC power system which has 5 cable
section. A larger system with multiple protection zones and multiple master-slave system
interaction with each other can provide redundancy to CFL functionality. To achieve the desired
CFL decision time with respect to the size of the power system would require multiple CFL units
interacting with each other. For example, with 1 master and 50 us cycle time, we can have
approximately 15 slaves connected in the topology. But in the real ship there may be a need for
77. 66
more than 15 slaves and hence having multiple CFL units interacting with each other can provide
the necessary 50 us cycle time
5.2.6 Sensitivity analysis of the differential protection scheme
Percentage differential protection (PDP) scheme used for fault identification and location
in the CFL system need to analyzed for sensitivity and adaptiveness of slope based on shipboard
power system operation. The values of restraint current and the minimum pickup current can be
modified to change the sensitivity of slope calculation.
78. 67
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