1. SHAHRIAR SEYEDHOSSEINI
709 Modern Ice Dr.
San Jose, CA
Phone : (408) 609-0516
shahriar_1359@msn.com
PUBLICATIONS
 US Patent for hardware implementation of LZW De-compressor (US 7071854)
EDUCATION
2003-2005 Villanova University - Villanova, PA
 Master of Science in Electrical Engineering
 Concentration in Digital Systems
1998-2002 Drexel University - Philadelphia, PA
 Bachelor of Science in Electrical Engineering
 Concentration in Signal Processing
 Third place in Senior Design Completion
2015 – Ongoing Stanford University, Palo, Alto, CA
Self-paced study
Related course work: CS193P, Developing iOS 8 Apps with Swift, and Machine Learning
PROFESSIONAL SUMMARY
Fifteen years of extensive experience in ASIC and Firmware verification at block and SoC level. Held leading and
management roles and successfully delivered number of FPGAs and ASIC projects (Custom FPGAs, PCIe root
complex IP, 40Gb MACs NBaseT PHY and 10GBaseT PHYs). Recognized for strong technical knowledge and
excellence in debugging skills. Highly experienced in architecting reusable verification environment, developing power
aware environments, and test cases in various methodologies and proficient in all stages of verification:
 Translate system level requirements into verification requirements
 Identify coverage points
 Development of constraint random verification plan and feature coverage requirements
 Design and development of modular, reusable, scalable and maintainable constraint random verification
environment
 Test stimulus generation and analysis
 SDF Gate level simulation and examination
 Pre-and post-silicon verification & debug to achieve verification goals
 Analysis of coverage results
 Developing Power Aware simulation environments using UPF through MVSIM and MVRC
 Lab bring up and debugaq_phi_env_config.sv
Deeply understand PCIe Gen1, 2 and 3 standard protocols (over 12 years of hands on experience with both RC and
endpoint devices) and has the knowledge about Ethernet, TCP/IP protocols.
Proficient in scripting to achieve high level of automation in verification process.
Skillful in C/C++ programing to debug and enhance firmware/driver.
Solid grasp of object oriented programing.
An independent android and iOS developer using Java (Current game has been downloaded more than 200,000
times from android market).
PROFESSIONAL SKILLS
 Verification Language: Systemverilog, Veilog HDL, Specman e, Vera
 Low Power Verification: UPF, MVSIM, MVRC
 Verification Methodology: UVM, OVM
 Simulators: Synopsys VCS, Cadence NC-Verilog, Mentor Questa and ModelSim
 VIPs: Denali memory models, Denali PCIe VIP (Purespec), Denali PCIe Puresuite
 Other Tools: Synopsys DVE, Simvision, Debussy, Sun Grid Engine, Bugzilla, Testopia
 Standard: PCIE Gen1/2/3, Ethernet, TCP/IP and PCI
 Programing Languages: C/C++, Java, Swift
 Scripting Languages: Perl, Python, TCL and shell scripting
 Scoping Tools: PCIe and PCI bus analyzer and Exerciser, logic analyzer

2. EXPERIENCE DETAILS
Aquantia (Startup) Milpitas, CA
Principal Technical Member of Staff Oct 2012 – Present
Active participant in architectural group for the new ASIC.
Verified PCIe and DMA engines as well as Transmit Protocols Offload module for the current project.
Customer (Intel Corporation) point of contact for technical issues related to 10GBaseT PHY.
Verified the new NBaseT PHY (2.5G and 5G) as well as 10GBaseT PHY (mixed signal Analog/Digital/DSP ASIC).
Performed low power simulation of the entire chip (more than 7 power domain, and many power gating logic).
Verified that all isolation cells are working correctly, and all pass through signals are working even through power
domains they cross are off.
Helped in chip bring up, and firmware debug. Found few asynchronous bugs in lab between analog domain and
digital domain on time and prevented chip re-spin.
Developed firmware’s clock and reset functions for NBaseT PHY.
Chelsio Communications (Startup) Sunnyvale, CA
Senior Technical Member of Staff - Verification Manager May 2007 – Oct 2012
Managed a team of four mid to senior verification engineers.
Designed and implemented the complete verification environment from scratch for a Multi PF(8)/VF(128) SRIOV
enabled Gen2/Gen3 PCIE module and a Scatter Gather Engine with multi-channel DMA Engines.
Developed host driver, and host memory models.
Performed full chip integration, and script developments.
Executed lab debugs and provided support to driver and firmware groups.
Electrolux Webster City, IA
Cost Engineer – Project Manager May 2006 – May 2007
Worked with Purchasing director and suppliers to implement various cost out projects to reduce the final cost of
parts. Achieved an estimated $2M saving for the company in a period of one year.
SPTEK Downingtown, PA
Cofounder, and CEO Sept 2005 – Jan 2006
Tried to use wireless sensor networks to reduce energy consumption (in terms of heat and electricity) in homes
and commercial buildings.
Unisys Corporation Malvern, PA
Design and Verification Engineer Sept 1999 – May 2006
Participated in design and verification, as well as hardware prototyping efforts for many projects ranging from
multimillion gates ASIC, and FPGA to embedded programming.
Designed and implemented many modules such as PCI target, PCI Bus Master, LZW De-compressor, Memory
Controllers, and other application specific components using both VHDL and VERILOG.
REFERENCE :
Professional references will be provided upon request
WORK STATUS:
US Citizen
HOBBIES:
Mobile Application development