Undergraduate course content: Introduction to microprocessors, The 8086 microprocessor architecture: Microprocessor ALSU functions Microprocessor 8 bits bus architecture Microprocessor 8/16 bits bus architecture 8086/8088 microprocessor registers 8086/8088 microprocessor instruction set RISC and CISC architectures External memory Tracing Program Codes Application Examples 8086 Interrupts Interrupt priority controller Microprocessor-based data communication

1. Microprocessor-Based Systems
Dr. Randa Elanwar
Lecture 7

2. Lecture Content
• Memory access: Fetch-Decode-Execution
• Tracing Program Codes
• Application Examples
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Microprocessor-Based Systems Dr. Randa Elanwar

3. Memory segmentation, address decoding
and direct access
• Since both the program and any subroutine use the same ALSU and
internal microprocessor registers, therefore, the current contents
may be destroyed. Thus, a copy of the contents should be saved in
stack to be re-copied back in sequence after the subroutine is
executed  PUSH instruction
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Microprocessor-Based Systems Dr. Randa Elanwar
CALL 600
CALL 7000
Main program
Subroutine 1
Subroutine 2
2000:120
2000:123
2000:600
650
653
7000
.
.
.
.
.
.
.
.
0653
0123
Stack
(memory
locations)
Stack
Pointer

4. 8086/8088 instruction set (CALL)
Unconditional Branch Instructions
• CALL: Unconditional Call: This instruction is used to call a subroutine from a
main program.
• In case of assembly language programming, the term procedure is used
interchangeably with subroutine. The address of the procedure may be
specified directly or indirectly depending upon the addressing mode.
• There are again two types of procedures depending upon whether it is
available in the same segment (Near CALL, i.e ± 32K displacement) or in
another segment (Far CALL, i.e. anywhere outside the segment).
• The modes for them are respectively called as intrasegment and
intersegment addressing modes. This instruction comes under
unconditional branch instructions and can be described as shown with the
coding formats.
• On execution, this instruction stores the incremented IP (i.e. address of the
next instruction) and CS onto the stack along with the flags and loads the CS
and IP registers, respectively, with the segment and offset addresses of the
procedure to be called.
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Microprocessor-Based Systems Dr. Randa Elanwar

5. 8086/8088 instruction set (RET)
• Unconditional Branch Instructions
• RET: Return from the Procedure: At each CALL instruction, the IP
and CS of the next instruction is pushed onto stack, before the
control is transferred to the procedure.
• At the end of the procedure, the RET instruction must be
executed.
• When it is executed, the previously stored content of IP and CS
along with flags are retrieved into the CS, IP and flag registers from
the stack and the execution of the main program continues
further.
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Microprocessor-Based Systems Dr. Randa Elanwar

6. 8086/8088 instruction set (PUSH-POP)
Data Copy/Transfer Instructions:
• PUSH: Push to Stack This instruction pushes the contents of the
specified register/memory location on to the stack.
• The stack pointer is decremented by 2, after each execution of
the instruction. The actual current stack-top is always occupied
by the previously pushed data. Hence, the push operation
decrements SP by two and then stores the two byte contents of
the operand onto the stack.
• The higher byte is pushed first and then the lower byte. Thus
out of the two decremented stack addresses the higher byte
occupies the higher address and the lower byte occupies the
lower address.
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Microprocessor-Based Systems Dr. Randa Elanwar

7. 8086/8088 instruction set (PUSH-POP)
Data Copy/Transfer Instructions:
• POP: Pop from Stack This instruction when executed loads
the specified register/memory location with the contents of
the memory location of which the address is formed using
the current stack segment and stack pointer as usual.
• The stack pointer is incremented by 2. The POP instruction
serves exactly opposite to the PUSH instruction.
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Microprocessor-Based Systems Dr. Randa Elanwar

8. 8086/8088 instruction set (PUSH-POP)
Data Copy/Transfer Instructions:
• PUSHF: Push Flags to Stack The push flag instruction pushes the
flag register on to the stack; first the upper byte and then the
lower byte will be pushed on to the stack. The SP is
decremented by 2, for each push operation. The general
operation of this instruction is similar to the PUSH operation.
• POPF: Pop Flags from Stack The pop flags instruction loads the
flag register completely (both bytes) from the word contents of
the memory location currently addressed by SP and SS. The SP
is incremented by 2 for each pop operation.
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Microprocessor-Based Systems Dr. Randa Elanwar

9. Memory access: Fetch-Decode-Execution
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Microprocessor-Based Systems Dr. Randa Elanwar
Programs
(Instruction
codes)
Data
Stack
External memory
divisions
SS: Stack segment register, holds the upper 16 bits
of the starting address for the program stack
SP: Stack pointer register, holds the offset of the
last location in the stack that has recently been
used for storage (top of the stack)
Example: main program
Address Instruction code meaning
2000:0111 E8 EC 00 CALL 200
2000:0114 ……. …….
.
.
.
2000:0200 50 PUSH AX
SS:SP

10. Memory access: Fetch-Decode-Execution
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Microprocessor-Based Systems Dr. Randa Elanwar
Address Instruction code meaning
2000:0111 E8 EC 00 CALL 200
2000:0114 ……. …….
.
.
.
2000:0200 50 PUSH AX
Note 1: Data direction is either TO or FROM
microprocessor
TO: means the microprocessor reads/gets data
on the bus
FROM: means the microprocessor
writes/sends data to the memory
Note 2: the instruction code status is either
FETCHED or EXECUTED
It is first FETCHED till all bytes are stored in
instruction registers then becomes EXECUTED.
Tracing the micro-operations:
Address Data To/from Microprocessor Fetch/Execute
2000:0111 E8 To (stored in IR0) FETCH
2000:0112 EC To (stored in IR1) FETCH
2000:0113 00 To (stored in IR2) FETCH
SS:SP-1 01(higher byte) From (store return add. in memory) EXECUTE
SS:SP-2 14(lower byte) From (store return add. in memory) EXECUTE
2000:0200 50 To (stored in IR0) FETCH

11. Memory access: Fetch-Decode-Execution
• The PUSH instruction saves the content of a 16 bits register into
the stack. For example, saving AX will require saving AH first
(decrement SP) then saving AL in the location on the top of it.
• AH has to be saved even if the microprocessor is operating in the
8-bit mode.
• The POP instruction restores the content of a 16 bits register from
the stack. For example, restoring AX will require restoring AL first
(8 bits) then restoring AH from the location next to it (increment
SP).
• The POP instruction restores data from the memory location which
offset is stored in SP.
• BP: Base Pointer, allows navigation within the stack to take copies
of the stored data without messing up with the data storage order.
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Microprocessor-Based Systems Dr. Randa Elanwar

12. Memory access: Fetch-Decode-Execution
• Important note:
• For more than 1 register, if we PUSH in some sequence we
POP in the reversed sequence.
• Example:
PUSH AX
PUSH DX
.
.
.
POP DX
POP AX
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13. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 0605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20
Subroutine 1 (13 instructions, 21 bytes)
140E:200 56 PUSH SI
140E:201 51 PUSH CX
140E:202 31 C0 XOR AX, AX
140E:204 02 04 ADD AL, [SI]
140E:206 80 D4 00 ADC AH, 0
140E:209 49 DEC CX
140E:20A E3 03 J CX Z 20F
140E:20C 46 INC SI
140E:20D EB F5 JMP 204
140E:20F E8 EE 00 CALL 300
140E:212 59 POP CX
140E:213 5E POP SI
140E:214 C3 RET
Subroutine 2 (6 instructions, 11 bytes)
140E:300 3C 40 00 CMP AX, 0040
140E:303 77 03 JA 308
140E:305 B3 00 MOV BL, 00
140E:307 C3 RET
140E:308 B3 01 MOV BL, 01
140E:30A C3 RET

14. Tracing Programs
• The aim of this program is to add the N elements of an array
(vector) and comparing the sum with 40 (Hex):
– If the sum > 40 store 1 in the memory location with offset 600
– If the sum < 40 store 0 in the memory location with offset 600
• The number of elements (array length) is stored in 2 bytes (603
and 604)
• In this example: the program, data and the stack are located in
the segment (140E), i.e., DS = SS = CS
thus we can differentiate between them through the range of
offsets:
Instructions (100  600), data (600  x) and stack (x  FFFF)
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Microprocessor-Based Systems Dr. Randa Elanwar

15. Tracing Programs
• The microprocessor to execute this program needs the
following:
1. Initialization to define the location of instructions, data and
stack
2. Know the number of array elements
3. Know the content of array
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Microprocessor-Based Systems Dr. Randa Elanwar

16. Tracing Programs
• Instructions from offset 104 to 105 forces the stack pointer to point
to the bottom of the stack (here the last location of the memory
segment 140E:FFFF)
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Microprocessor-Based Systems Dr. Randa Elanwar
MOV AX, CS
MOV SS, AX or
MOV DS, AX
MOV AX, CS
MOV SS, AX
PUSH CS
POP DS
Instructions from offset 100 to
108 store the value 140E in CS,
SS and DS (initialization)
MOV SS, CS Invalid instruction
This operation can be done by
one of two methods
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20

17. Tracing Programs
• Let the data stored in memory:
140E:600 xx xx xx 02 00 14 3C ………
• We need a counter = number of elements that is decremented on
each time we perform summation. Thus summation stops when the
counter = 0
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Microprocessor-Based Systems Dr. Randa Elanwar
8B 0F 03 06
MOV CX [0603]
The instructions from 109 to 10C
set the counter to the value
stored in the memory location
[0603]
[603]  CL and [604]  CH i.e.,
CL = 02 and CH = 00
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20

18. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
•We need the SI register to be
the source of data thus we
store the location of the first
array element in SI
(instructions from 10D to 10F)
•The instructions from 110 to
112 call a subroutine which
perform addition.
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20
•The instructions from 113 to 115 saves the final result of addition in the
location 140E:601 and 602 after the subroutines execution.
•The instruction 116 saves the result comparison in the location
140E:600 after the subroutines execution.

19. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Subroutine 1 steps:
•The instructions from 200 to 201 save
the contents of SI and CX in the stack
to avoid changes
•The instructions 202 and 203 clear the
content of AX
•The instructions 204 and 205 add the
contents of SI to AL and puts the result
back into AL
•The instructions from 206 to 208 add
with carry the contents of AH to zero
•The instruction 209 decrements the
counter CX (holding the number of
elements)
Subroutine 1 (13 instructions, 21 bytes)
140E:200 56 PUSH SI
140E:201 51 PUSH CX
140E:202 31 C0 XOR AX, AX
140E:204 02 04 ADD AL, [SI]
140E:206 80 D4 00 ADC AH, 0
140E:209 49 DEC CX
140E:20A E3 03 J CX Z 20F
140E:20C 46 INC SI
140E:20D EB F5 JMP 204
140E:20F E8 EE 00 CALL 300
140E:212 59 POP CX
140E:213 5E POP SI
140E:214 C3 RET

20. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Subroutine 1 steps:
•The instructions from 20A to 20B
checks if the counter CX value = zero
(i.e., end of array)
•If not yet, the instructions from 20C to
20D increment SI and jump back to 204
(i.e., repeat addition)
•If the counter CX value = zero (i.e.,
addition complete), the instructions
from 20F to 211 call the subroutine 2 to
compare the sum with 40 H
•The instructions 212 and 213 restore
the initial values of CX and SI
•The instructions 214 returns to the
main program
Subroutine 1 (13 instructions, 21 bytes)
140E:200 56 PUSH SI
140E:201 51 PUSH CX
140E:202 31 C0 XOR AX, AX
140E:204 02 04 ADD AL, [SI]
140E:206 80 D4 00 ADC AH, 0
140E:209 49 DEC CX
140E:20A E3 03 J CX Z 20F
140E:20C 46 INC SI
140E:20D EB F5 JMP 204
140E:20F E8 EE 00 CALL 300
140E:212 59 POP CX
140E:213 5E POP SI
140E:214 C3 RET

21. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Subroutine 2 steps:
•The instructions from 300 to 302
compare the contents of AX to 0040
•If the sum is below 40, the
instructions from 305 to 306 make BL
content = zeros and return to
subroutine 1
•If the sum is above 40, the
instructions 303 jump to instruction
308 and the instructions from 308 to
309 make BL content = 01 and return
to subroutine 1
Subroutine 2 (6 instructions, 11 bytes)
140E:300 3C 40 00 CMP AX, 0040
140E:303 77 03 JA 308
140E:305 B3 00 MOV BL, 00
140E:307 C3 RET
140E:308 B3 01 MOV BL, 01
140E:30A C3 RET

22. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
FETCH EXECUTE (From
memory)
RESULT
MOV AX, CS 2R  IR0, IR1 --- AX=140E
MOV SS, AX 2R  IR0, IR1 --- SS=140E
MOV SP, FFFF 3R  IR0, IR1, IR2 --- SP=FFFF
PUSH CS 1R  IR0 2W to stack 140E:FFFE= 14
140E:FFFD= 0E
SP=FFFD
POP DS 1R  IR0 2R from stack DS=140E
SP=FFFF
MOV CX, [0603] 4R  IR0, IR1, IR2, IR3 2R [0603 is an offset] CX=0002
MOV SI, 605 3R  IR0, IR1, IR2 --- 605 is a number SI = 0605
CALL 200 3R  IR0, IR1, IR2 2W Ret. Add. In stack SP=FFFD
PUSH SI 1R  IR0 2W to stack SP=FFFB
PUSH CX 1R  IR0 2W to stack SP=FFF9

23. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
FETCH EXECUTE (From
memory)
RESULT
XOR AX, AX 2R  IR0, IR1 --- AX = 0
ADD AL, [SI] 2R  IR0, IR1 1R (from 0605) AL = 14
ADC AH, 0 3R  IR0, IR1, IR2 --- AX = 0014
DEC CX 1R  IR0 --- CX = 01
JCXZ 20F 2R  IR0, IR1 --- ---
INC SI 1R  IR0 --- SI = 606
JMP 204 2R  IR0, IR1 --- ---
ADD AL, [SI] 2R  IR0, IR1 1R (from 0606) AL = 14+3C = 50
ADC AH, 0 3R  IR0, IR1, IR2 --- AX = 0050
DEC CX 1R  IR0 --- CX = 00
JCXZ 20F 2R  IR0, IR1 --- ---
CALL 300 3R  IR0, IR1, IR2 2W Ret. Add. In stack SP=FFF7

24. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
FETCH EXECUTE (From
memory)
RESULT
CMP AX, 0040 3R  IR0, IR1, IR2 --- Change Flags
JA 308 2R  IR0, IR1 --- ---
MOV BL, 01 2R  IR0, IR1 --- BL = 01
RET 1R  IR0 2R (POP Ret. Add.) SP=FFF9
POP CX 1R  IR0 2R from stack SP=FFFB
POP SI 1R  IR0 2R from stack SP=FFFD
RET 1R  IR0 2R from stack SP=FFFF
MOV [601], AX 3R  IR0, IR1, IR2 2W to [601], [602] [601]=50
[602]=00
MOV [600], BL 4R  IR0, IR1, IR2, IR3 1W to [600] [600]=01

25. Tracing Programs
• Example: Trace the following instruction
• 3E3F:21F 51 PUSH CX
• Given that: CX=0ABD, SS=3E3F, SP=FFF0
• Fetch: 1R from address: 3E60F to IR0
IP = 220 (next address: 21F+1)
• Execute: 2W to stack
SP-1  3E3F:FFEF = 0A  CH
SP-2  3E3F:FFEE = BD  CL
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Microprocessor-Based Systems Dr. Randa Elanwar
Start 3E3F0
+
Offset 021F
Address 3E60F

26. Tracing Programs
• Example: Trace the following instruction
21BD:0182 83 80 06 70 0F 00 ADD WordPtr[SI+BX-7ABC], 000F
• Given that: SI=E000, BX=0AC2, DS=2100
• Memory contents: 21BD:6430 00 12 34 56 78 9A BC DE
• Fetch: 6R from addresses 21BD:0182 – 0187 to IR0 – IR5
Physical address:
Therefore, 1st operand = DE BC, 2nd operand = 00 0F
Addition Result = DECB
• Execute: 2W to memory
2100:7006 = CB
2100:7007 = DE
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Microprocessor-Based Systems Dr. Randa Elanwar
Offset
SI E000
+
BX 0AC2
EAC2
-
7ABC
7006
DS 21000 28006
+ -
Offset 7006 21BD0
28006 6436

27. Tracing Programs
• Example: Trace the following instruction
• 3130:02BD FF 54 xx CALL [SI-07]
• Given that: SI=206, DS=2150, SS=2930, SP=FF00
• Memory contents:
2130:03F0 00 00 00 01 00 02 00 03 FF FF 00 00 01 02 03 00
2130:0400 04 00 9A 25 02 33 26 83 C4 02 89 46 C6 89 56 F8
• Fetch: 3R from addresses 2130:02BD – 02BF to IR0, IR1, IR2
IP = 2C0 (next address: 2BF+3)
• Execute: 6W into stack
SP-1  2930:FEFF = 02  IPH
SP-2  2930:FEFE = C0  IPL
SP-3  2930:FEFD = 31 CSH
SP-4  2930:FEFC = 30  CSL
SP-5  2930:FEFB  FlagsH
SP-6  2930:FEFA  FlagsL
2R (calling subroutine address) from
2150:01FF = 2130:03FF  IPL = 00
2150:0200 = 2130:0400  IPH = 04
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Microprocessor-Based Systems Dr. Randa Elanwar
Offset
SI 0206
-
07
1FF
DS 21500 216FF
+ -
Offset 1FF 21300
216FF 3FF