Ziptillion boosting RISC-V with an efficient and os transparent memory compression system

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December 8-10 | Virtual Event

Ziptilion™️: Boosting RISC-V with an Efficient and OS
Transparent Memory Compression System
Angelos Arelakis
Co-founder and CTO
ZeroPoint Technologies
#RISCVSUMMIT

About ZeroPoint Technologies Prof. Per Stenström
CSO, Co-founder/inventor
Internationally renowned memory architecture expert (ACM and
IEEE Fellow).
Professor at Chalmers University of Technology. Senior industry
experience from Sun Microsystems with a wide industry network.
Dr. Angelos Arelakis
CTO, Co-founder/inventor
Memory system architecture and ultra-fast data
compression expert.
Has received award from the King Carl XVI Gustaf’s
fund for science, technology and environment.
15 people strong R&D team:
• State of the Art Compression
Algorithm Research & Development
• Memory Architecture Optimization
• Linux Kernel Development
• High Volume ASIC/FPGA
Development and Manufacturing
The Main Memory Compression Invention
originates from Prof. Per Stenström in the
late 1990’s
Company founded 2016, by
Prof. Per Stenström and Dr. Angelos Arelakis
Real Time Memory Compression is a
Challenging problem and Hard to solve
ZeroPoint’s achievement is the result of:
• Decades of frontline research
• In-depth knowledge
• Unique mix of competencies
50 manyears invested in R&D

System performance scaling, as we knew it,
stopped due to a Moore’s Law and Dennard’s
Scaling decline.
Heterogenous Multi-Processor Systems
continue to deliver compute power, but the
memory hierarchy cannot keep up.
The computing system scaling challenge
40 years of Microprocessor Trend Data Image: Karl Rupp

stopped due to Moore’s Law and Dennard’s
Scaling decline.
Applications demand ever increasing memory
capacity and bandwidth

stopped due to Moore’s Law and Dennard’s
Scaling decline.
Applications demand ever increasing memory
capacity and bandwidth
Memory
compression can
bridge the gap
We need new and disruptive solutions

ZeroPoint’s product – Ziptilion™️
Value proposition
• ZeroPoint Technologies: The only real time memory compression
technology
• Ziptilion doubles the memory capacity
• Ziptilion doubles the effective memory bandwidth

CPU(1)
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DRAM ctrl
ZiptilionTM
DRAM ctrl
ZiptilionTM
CPU(n)
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DIMM DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
GPU
Peripherals
I/O
Other
M a i n M e m o r y
C o m p r e s s i o n
Ready for Tape Out in
EuroEXA* (800MHz @28nm)
• General purpose and lossless
• 2-3x compression performance
• Fast – Real time
• Compact – Area efficient
• Strong patent portfolio (10 patent families)
and a pipeline of new innovations
*funded by European Union, Horizon2020 program
EuroEXA builds an HPC system
ZeroPoint’s product – Ziptilion™️
The only real time Memory Compression Technology

Ziptilion™️ IP building blocks and latency
• Read and write data paths are
pipelined to sustain high throughput
to/from memory
• #Compressors/#Decompressors
configurable based on the target
memory b/w requirements
• Address translation: TLB-like block
translates on-the-fly from the physical
to the compressed address space
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ZiptilionTM
DRAM ctrl
ZiptilionTM
CPU(n)
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L1D$ L1I$
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DIMM DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
GPU
Peripherals
I/O
Other

Ziptilion™️ IP innovations
Low overhead compression-related metadata:
0.7-3% of memory depending on IP configuration
Efficient compression algorithms optimized to
minimize latency and increase compressibility
Hardware-accelerated and online memory and
traffic data analysis to tune compression
Hardware / Software synergy offers robust
management of the compressed memory

Ziptilion™️: Transparent integration to the
operating system (OS)
• Ziptilion IP is integrated in the memory access path
and compresses the data continuously
• Free memory space generated by Ziptilion IP
(hardware) is collected by the Ziptilion SW driver
• Ziptilion SW forms a page-oriented pseudo-RAM
device (VPC)
• VPC exposed to OS transparently by connecting the
Ziptilion SW driver to the Frontswap API

Ziptilion™️ VPC vs state-of-art vs baseline
Baseline uncompressed memory

State-of-art ZSWAP/ZRAM

Ziptilion VPC

Ziptilion: Compression algorithms implemented in
hardware today
Ziptilion+: Next IP generation
1
1.5
2
2.5
3
3.5
4
Compression
Ratio
(times)
SPEC2017
Memory compressibility with Ziptilion and Ziptilion+
Ziptilion
Ziptilion+
Compression ratio for SPEC2017
SPEC2017INT SPEC2017FP
• Ziptilion: Compresses SPEC2017 on average by
2.2x
• Ziptilion+: More applications are compressed by >2x
23.4
27.6
Ziptilion IP offers important compression opportunities: 2.2-2.6x

Ziptilion: Compression algorithms implemented in
hardware today
Ziptilion+: Next IP generation
Compression ratio for MLPerf/Training
Promising compression for MLPerf/Training workloads: 2.5x-3x

• No Ziptilion / 1x memory: Baseline system
without Ziptilion. Memory is adjusted to fit 50% of
the application’s memory footprint
• Results are normalized to this baseline
• Ziptilion / 1x memory: Above baseline system
enhanced with Ziptilion
• No Ziptilion / 2x memory: Baseline system
without Ziptilion and with enough memory to fit
the application footprint in memory
Ziptilion™️ performance for SPEC2017
Ziptilion offers 20% higher performance
Performance improvement close to a system with 2x more physical memory

ZSWAP+/ZRAM+: ZeroPoint hardware
accelerated ZSWAP/ZRAM
Baseline ZSWAP/ZRAM swap out
Baseline ZSWAP/ZRAM swap in

• Lightweight Ziptilion IP containing mainly
compression and decompression accelerators
integrated in the memory access path
• ZSWAP/ZRAM API is modified to call the
hardware accelerators instead of SW-based
compression
Operation ZSWAP+/ZRAM+
Compression acceleration 15x
Decompression acceleration 10x
10-15x faster ZSWAP/ZRAM compression & decompression
crypto_compress_(a)comp
API
HW accelerated
ZComp
HW accelerated
ZDecomp
crypto_compress_(a)comp
API

ZSWAP+/ZRAM+
• HW accelerated ZSWAP/ZRAM
• Superfast, low power ZRAM/ZSWAP device
• Supporting Android and Linux based platforms (Smart
devices, Laptops and Servers) that benefit from a hardware
accelerated compressed swap device
ZSWAP+/ZRAM+
Entry version
Speed: 1.4x speed-up
License: Free of charge License
ZSWAP+/ZRAM+
Performance version
Speed: 2x speed-up
License: Paid License
Available
Q1-2021
Contact ZeroPoint for evaluation!

Compression+Encryption
The cost of security is negligible when combined with compression
Standard encryption algorithms such as AES-XTS and new ciphers such as PRINCE

• Mature product –
Transparent integration to OS and Application
• Typically IP size: ~0.4mm2 @7nm
• High Performance and High Security –
Combining Compression and Encryption
Server CPU customer
“DRAM is super expensive!”
50% increased Performance / Watt
Performance:
Bandwidth:
Capacity:
20-50% increased System
Performance
Up to 50% increased available
Memory Bandwidth
2-3x increased Memory Capacity
ZeroPoint technology delivers
significant customer value

Thank you for joining us.
Contribute to the RISC-V conversation on social!
#RISCVSUMMIT @risc_v

Ziptillion boosting RISC-V with an efficient and os transparent memory compression system

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Ziptillion boosting RISC-V with an efficient and os transparent memory compression system