RISC-V 30910 kassem_ summit 2020 - so_c_gen
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This document proposes a no-human-in-the-loop open-source "idea to manufacturing" SoC compiler. It consists of SoCGen, which generates RTL from a JSON description, and OpenLANE, which produces a clean GDSII layout from the RTL with no human intervention. SoCGen includes a library of open-source verified IP cores and supports multiple bus architectures. OpenLANE uses carefully-curated open-source EDA tools tuned for an open PDK. The goal is to streamline and automate the entire custom SoC design process from concept to silicon to enable more widespread adoption.
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RISC-V 30910 kassem_ summit 2020 - so_c_gen
- 1. A Complete no-human-in-the-loop Open-Source "Idea to Manufacturing" SoC Compiler Mohamed Shalan (mshalan@aucegypt.edu) Mohamed Kassem (mkk@efabless.com)
- 2. Introduction ● Custom SoC development is a complex expensive process ▪ Not good for deeply embedded devices ● Large varieties of microcontrollers are out there to address different requirements for embedded applications ● Some embedded applications can benefit from custom SoCs ▪ Custom accelerators, lower power, custom form factor, new sensors, … ▪ Needs to simplify the design process to enable wider impact
- 3. Custom SoC Development ● How to enable it for deep embedded system designers? ▪ Lower Cost: Engineering, Tools, IPs, SW, … ▪ Shorter time to market ▪ Streamlined design process from RTL to a manufacturable GDSII
- 5. SoC Design Automation Flow JSON SoCGen RTL PDK OpenLANE GDSII IP Lib
- 6. Benefits ▪ Facilitate automatic SoC design (RTL to clean GDSII) ▪ Reduce time and effort to fabrication ▪ Enable Rapid Design Space Exploration ▪ Promote Design Reuse
- 7. SoCGen JSON SoCGen RTL + TB PDK IP Lib • Peripherals • Masters • Bus Components DDs DOCs
- 8. SoCGen
- 9. SoCGen IP Library ▪ JSON descriptions and Verilog HDL for open-source verified IPs ▪ Examples: GPIO, UART, I2C master, SPI master, timer, PWM, Memory controllers, … ▪ Can be bus-specific or generic ▪ Bus wrappers are auto-generated
- 10. SoCGen ● Supported Buses: AHB-Lite, APB and Wishbone ● Masters: Any master with supported bus interfaces can be used after creating a JSON description file ● Different topologies: ▪ Multiple Masters on the same high performance bus ▪ One Master on different high performance busses ▪ Multiple sub-busses on the same high performance bus
- 11. SoC Design Automation Flow JSON SoCGen RTL PDK OpenLANE GDSII IP Lib
- 12. OpenLANE ▪ Main Goal: Produce a clean GDSII with no human intervention (no- human-in-the-loop) ▪ Clean means: Manufacturable and testable ▪ No LVS Violations ▪ No DRC Violations ▪ Timing Violations? WIP - engineered margins
- 13. OpenLANE ● Started as an Open-Source Flow for a True Open Source Tape-out Experiment ● striVe is a family of open everything SoCs ▪ Open PDK, Open EDA, Open RTL, Open GDSII ▪ Design verification setup is included
- 15. OpenLANE ▪ Main Goal: Produce a clean GDSII with no human intervention (no-human-in-the-loop) ▪ Open Source (Apache 2.0) ▪ Tuned for SKY130A Open PDK by SkyWater ▪ Can be used to harden Macros and SoCs ▪ Two modes of operation: Autonomous or Interactive ▪ Design Space Exploration
- 17. OpenLANE ● 16 “carefully-curated” EDA tools from different projects ● Swiss Army Knife (SAK) with 70+ utilities: Pre-processing, Optimization, Abstraction of views, etc. ● For the savvy designer - 40 design/flow configurations ● More than 40 open-source designs with their known zero-DRC configurations
- 18. OpenLANE ● GH repo became public on July 20, 2020 ● 4 Months Later: ▪ 1400 Unique Clones ▪ 180 Stars ▪ 41 Forks ▪ …
- 19. OpenMPW Program + • Standard Harness Setup • Management/User resources • 40 open slots • ~100 parts & 5 harness boards Caravel SoC User Space First: Nov 30, 2020 More in 2021 github.com/efabless/caravel
Hinweis der Redaktion
- Embedded SoC needs to be cheap to suite application agreesive cost requirements. Large number of microcontrollers are available to How to enable SoC design
- To laverage OS H/W