Low power cost rns comparison via partitioning the dynamic range

CONTACT: PRAVEEN KUMAR. L (,+91 – 9791938249)
MAIL ID: sunsid1989@gmail.com, praveen@nexgenproject.com
Web: www.nexgenproject.com, www.finalyear-ieeeprojects.com
Low-Power/Cost RNS Comparison via Partitioning the
Dynamic Range
Abstract:
Residue number systems (RNSs) are the main choice in many comparison- and division-free
applications (e.g., digital signal processing). However, the development of efficient RNS
comparators can widen the spectrum of RNS applications. Such comparators can replace the
straightforward, but slow and costly, practice of converting the comparison operands to binary,
as inputs to a wide word binary comparator. This has motivated some researchers to design
shortcut RNS comparison methods that obviate the need for full reverse conversions. However,
the few actual realizations that we have encountered are based on moduli set τ = {2n − 1, 2n, 2n
+ 1}. In this paper, after brief review and performance evaluation of the previous methods, we
present a new τ -comparator with considerably reduced cost and power dissipation, with no delay
penalty. The underlying comparison algorithm is based on ordering the dynamic range into
consecutive partitions, and locating the partitions that own the corresponding comparison
operands. The required circuitry includes two n-bit adders, which are replaced by one compound
parallel prefix architecture, in order to save area and power. Postlayout performance evaluations,
of the proposed work and the best previous one, show small latency improvement, 17 %( 46%)
reduction in area consumption, 30 %( 41%) in power dissipation, and 31 %( 47%) in power-
delay product, for n = 8(22). The proposed architecture of this paper analysis the logic size, area
and power consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
Residue number systems (RNS) have been for a long time a topic of intensive research. Their
usefulness has been demonstrated, especially for computations where additions, subtractions and
multiplications dominate, because such operations can be done independently for each residue
digit without carry propagation. Other operations such as overflow detection, sign detection,
magnitude comparison and division in RNS are very difficult and time consuming. However,
above mentioned operations are essential in certain applications, e.g. in exact arithmetic or

computational geometry, where residue arithmetic is applied. RESIDUE number system (RNS)
is an ancient numerical representation system. It is recorded in one of Chinese arithmetical
masterpieces, the Sun Tzu Suan Jing, in the 4th century and transferred to European known as
Chinese Remainder Theorem (CRT) in the 12th century. RNS is a non weighted numerical
representation system and has carry-free property in multiplication and addition operations. In
recent years, it has been received intensive study in the very large scale integration circuits
(VLSI) design for digital signal processing (DSP) systems with high speed and low power
consumption.
An RNS is characterized by a set of k pair wise relatively prime moduli mk–1 > . . . > m1 > m0
and a residue set Ri for the ith modulus, typically chosen to be [0, mi). Clearly, at most one of
the moduli can be even and that one is usually taken to be a power of 2 to simplify the associated
circuitry; all other moduli are odd. Roughly speaking, the set of moduli corresponds to the choice
of a radix and the residue set to the digit set of positional fixed-radix number representations.
Just as the digit set of nonredundant radix-r system can be chosen to be [a, r + a), a < 0, the
residue set Ri associated with mi can be selected to be [ai, mi + ai). Such nonredundant RNS
have been extensively studied and used, primarily, in signal processing applications. An RNS
may have a handful of large moduli, typically chosen to be integers of the form 2h or 2h ± 1, or a
larger number of small moduli, often chosen to be primes or powers of primes. The former
category of RNS corresponds to very-high-radix number representation systems, in which digit
manipulation circuits are quite complex but there are fewer such circuits, while the latter are akin
to moderately high radices such as 16 or 64.
The primary advantage of RNS is that addition, subtraction, and multiplication can be performed
independently and in parallel on the various residues. When the residues are small, this results in
very high speed, particularly for multiplication which is slow / expensive with conventional
number representation.
Disadvantages:
 high the area consumption
 high the power consumption
 high the PDP
Proposed System:

Given the long standing popularity of the τ set and the few actual RNS comparator realization
that we have encountered (besides the one with parity checking method) are on τ, we also present
our scheme on τ , where m1 = 2n − 1, m2 = 2n, and m3 = 2n + 1, with dynamic range M = m1m2m3
= 2n(22n − 1).
Define the partitioning function p1(X): X = (x1, x2, x3) → s1, where X ∈ [0, M), xi = |X|mi, and s1
∈ [0, m1) identifies the sub-range that owns X. Table III describes such partitioning by m1, where
M1 = m2m3, and S0 to Sm1−1 denote the partitions.
Consequently, comparison of two unequal RNS numbers X = (x1, x2, x3) and Y = (y1, y2, y3) can
be reduced by comparing p1(X) and p1(Y). However, p1(X) = p1(Y) does not imply that X = Y.
Therefore, we can extend the partitioning of each primary subrange to m2 secondary subranges,
with partitioning function p2, where comparing p2(X) and p2(Y) leads to the desired result, except
for the case of p2(X) = p2(Y). In this case, comparison of x3 and y3 yields the final comparison
result.
Implementation of p1 and p2
TABLE I FOUR-OPERAND ADDITION FOR p1(X)
Table I contains the constituent bits of the four-operand modular addition that computes p1(X),
where x1 = an−1 ... a0, x2 = bn−1 ... b0, and wn is the carry-out of a simple n-bit adder that computes
p2(X) = w. We use an array of 4/2Cs to reduce the number of operands to two, and use a modulo-
(2n − 1) adder to obtain the final sum. However, to speed up this process, we use two different 4
/2Cs for position 0 of Table I regarding the two possible values of wn, and accordingly two
modular adders, as shown in Fig. 1. The output of these adders is multiplexed through wn to lead
to the desired p1(X).

Fig. 1. p1(X) and p2(X) generators.
Having generated p1 and p2 values for the two comparison operands X = (x1, x2, x3) and Y = (y1,
y2, y3), the final comparison result can be obtained via the termination circuitry, as shown in Fig.
2, where E outputs denote equity of comparator inputs and C outputs satisfy C = 1(0) if X > Y (X
≤ Y ).
Fig. 2. Generation of comparison result.

PARALLEL PREFIX REALIZATION
The modular adders of Fig. 1 can be replaced by fast parallel prefix modulo-(2n −1) adders in
order to achieve faster comparators. Fig. 3 shows the required compound adder, where the
functions of circuit symbols with more than one occurrence are also illustrated and those of the
four singletons are described through their corresponding output expressions below.

Fig. 3. Compound parallel prefix adder and its basic cells
Advantages:
 Reduce the area consumption
 Reduce the power consumption

 Reduce the PDP
Software implementation:
 Modelsim
 Xilinx ISE

Low power cost rns comparison via partitioning the dynamic range

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