1. EXPERIENCE
Data Channel Staging Engineer – Co-op
HGST Inc, Rochester, MN May ’14 – January ‘15
 Evaluated the effectiveness of advanced data recovery procedures, noise reduction calibration and compensation networks
 Measured the data channel’s performance using BER and error margins based on data convergence at LDPC decoders
 Wrote scripts to analyze the performance of LDPC decoders for trapping sets and near code-words
 Worked on advanced adaptive noise predictors / noise calibrators for the high speed data channel
Embedded Engineer
Robert BOSCH Engineering& Business Solutions Limited, India September ’10 – July ’13
 Designed runtime optimized low level drivers for a multi-core processor as a part of MicroController Abstraction Layer (MCAL)
 Participated in re-designing of existing MCAL for multi-core controlled based on PowerPC architecture
 Implemented drivers for ECU’s in generating complex waveforms for Ignition and Injections of an IC engine
EDUCATION DETAILS
 Master of Science in Electrical and Computer Engineering Expected Graduation – May ’15
University of Minnesota – Twin Cities, Minneapolis, MN, USA GPA – 3.60 / 4.00
Specialization: Communications and Signal Processing
Key Courses: Probability Theory, Digital & Wireless Comm.., Multi-rate Signal Processing, Detection Theory, ITC and DSP Algorithm & Design
 Bachelor of Engineering in Electronics and Communication Engineering May ‘10
Visvesvaraya Technological University, Belgaum, India
Project Work: “Character Recognition” – A Neural Network based hand written script recognition system
SKILL SET
Programming Language: C, Embedded C, C++, ASM and MATLAB
Scripting Language: LA
TEX, PERL and Tcl
Microcontroller Programming: Infineon’s 17XX, Freescale’s 567XX
DSP Algorithm Design & Implementation: Texas Instrument’s FPGA XC3S500E
Communication Protocols: SPI and Microsecond Channel
Proficient with Windows and Linux (Attended RHCSA training) operating systems
ACADEMIC PROJECTS & PRESENTATIONS
 OFDM Implementation for a MIMO system UMN - Ongoing
Designing and implementing an OFDM transceiver for a MIMO system on Spartan3E XC3S500E FPGA kit.
 12 X 8 Multiply & Accumulator UMN – February ‘15
Implemented a 12 X 8 MAC unit for a fixed point floating arithmetic on Spartan3E XC3S500E FPGA kit
Evaluated the accuracy of the MAC unit using ChipScope
 Ultra Sound Signal Enhancement using Curvelet Transform UMN – March ‘14
Applied a bi-orthogonal Curvelet transform on ultrasound signals to improve quality of ultrasound imaging as compared
to the conventional wavelet processing
 LTE Uplink UMN – May ’14
In class presentation on PHY layer of LTE Uplink protocol.
 Analysis of low-dimensional structure in high-dimensional data using PCA UMN – October ‘13
Interpretation / visualization of the multivariate Gaussian distribution to cases where the covariance matrix is rank
deficient for representing high-dimensional data into a lower dimensional subspace of estimators
 Discrete Time Wiener Filtering for Digital Signal Processing UMN – November ‘13
Applied wiener filtering technique to recover a noisy signal in a case where the noise estimate was absent
 Performance Analysis of Viterbi and other Linear Equalizations UMN – November ‘13
Implemented Viterbi algorithm for a multipath channel and compared its performance against the performances of
MMSE, MSE and ZF equalizers
PRADHAN BELLAM
986, 15th AVE SE, APT 3, Minneapolis, MN - 55414
bella126@umn.edu || (612)402-0260