1. Intel® Itanium® Hotchips 2011 Overview

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p g , y g ,
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Copyright © 2011 Intel Corporation. All rights reserved.
All dates and plans are subject to change without notice.

3. Itanium® Update
p
• Committed Itanium Roadmap
• Itanium® 9300 Processor delivered in 2010
• Poulson, the 10th Itanium processor, is on track for 2012 delivery
• Kittson processor under development
• Intel® Itanium® Processor Line delivers Mission Critical UNIX support,
with mainframe-class reliability and scalability
ih i f l li bili d l bili
• Itanium-based Solutions are a $4B industry in Mission Critical
computing
(1)
More than 80% top Global 100 companies running Itanium®
(1) Source: Hewlett-Packard, 2010
3 All dates and plans are subject to change without notice.

4. Poulson: Advances Itanium® Architecture
Key Highlights
• New architecture, 2x the cores,
2x instructions throughput
• Total 54MB on-die memory
• 3.1 Billion Transistors on 32nm process
Key Capab t es
ey Capabilities New!
• Intel® Instruction Replay Technology
• Intel® Hyper-Threading Technology, enhanced
with dual-domain multi-threading support
• Intel® Itanium New Instructions
Poulson: the most sophisticated Intel® processor to date
4 All dates and plans are subject to change without notice.

5. Poulson: First Intel Processor to support
Intel® Instruction Replay Technology
p y gy
Instruction
Buffer
Replay pipeline path
Instruction replay capability improves system resiliency
• Expanded error detection captures more errors in various stages
• Errant instructions are then re executed from Instruction buffer to
re-executed
automatically recover from severe errors
Intel® I t ti R l T h l
I t l® Instruction Replay Technology helps to prevent
h l t t
system crashes and data corruption
5 All dates and plans are subject to change without notice.

6. Greater Parallelism with Intel®
Hyper-Threading Technology Improvements
yp g gy p
Front-End Back-End
Instruction
Instruction
i
Buffer
Buffer
Dual-Domain Multithreading support enhances performance
• Minimizes thread switching costs of traditional Itanium MT implementation
• Maximizes efficiency of concurrent threads to complement
12-issue instruction execution
Unique EPIC architecture implementation to
increase overall throughput
6 All dates and plans are subject to change without notice.

7. Itanium® Processor New Instructions
Mid- Branch Floating Point
Mid-
Expanded Data Level Predict Execution
Inst.
Level Integer Operations
Access Hints Cache
BR Integer Floatin Data
• mpy4
• mov dahr CTL Register
R i t g Pt RF Cache
C h
• mpyshl4
1st
Integer • clz
struction
level
Cache Execution
Queues
1st
Ins
level 1st level
Cache Cache
Buffers
Thread Control Pipe Line Interface Expanded Software
Buffers
• hint@priority Control Logic Prefetch
• if t h
ifetch.count
t
Individual Poulson Core
• Poulson continues to optimize for legacy Itanium code without recompilation
• New Instructions simplify common tasks and branch operations to help take
future Itanium performance to the next level
Poulson architecture and New Instructions are underpinnings
i i i i
for the future of Itanium computing
7 All dates and plans are subject to change without notice.

8. Poulson RAS Advances Increase
System and Application Resiliency
Error Prevention and End to End Error Improved Firmware
Correction Detection Error Handling
• Intel® Instruction Replay • Enhanced Cache error • Expanded coverage of
Technology coverage p
potential error events
for automatic recovery
• Expanded use of soft • Residual error
error resilient structures protection for floating- • Improved logging and
point operations configurations for
• HW/SW mechanisms
higher
hi h availability and
il bilit d
enable correctable parity
serviceability
errors
Increases Process Improves Execution Minimizes Service
Resiliency Integrity Interruption
Enables mission critical RAS capability with enhanced error
prevention, detection and correction
8 All dates and plans are subject to change without notice.

9. Poulson Builds on Itanium’s Strengths
• Intel® Itanium New Instructions
New Itanium • Intel® Hyper Threading Technology improvements
Intel Hyper-Threading
Architecture • Doubles the high capacity cores and
delivers maximum 12-issue execution EPIC architecture
• Intel® Instruction Replay Technology
Improved Power
• Enables accurate Core power prediction and management
Management and
RAS features • Achieves mainframe reliability and resiliency with high levels
of RAS feature integration
• Intel’s most sophisticated general purpose processor to date
Innovative with 3 1B transistors
3.1B
engineering work • Supports advanced OEM system features for physical
partitions, seamless failovers, and system reconfigurations
Strong Foundation for the future of Itanium Computing
9 All dates and plans are subject to change without notice.

10. Thank You