1. Geometry induced crosstalk reduction in carbon nanotube interconnects
P. Uma Sathyakam, Paridhi Singh, Priyamanga Bhardwaj and P. S. Mallick
School of Electrical Engineering, VIT University, Vellore, Tamil Nadu, 632014, India.
E-mail: umasathyakam.p@vit.ac.in; psmallick@vit.ac.in
CNT Bundle Geometry: Traditionally, copper interconnects were treated as
rectangular or square cross sectioned interconnects which is essentially true for
dual damascene CMOS process [5]. On the other hand, CNTs are grown first on a
substrate and then densified into vertical or horizontal pillars [16]. It is shown
that the metal contact, on which CNTs are grown, can be patterned according to
the bundle width [17]. So, we take the advantage of the fact that CNT bundles
can be grown in various geometries depending on the contact pattern geometry.
(a) (b)
Fig. 1 CNT bundle geometries considered in this paper. (a) Square CNT bundle, (b)
Triangular CNT bundle.
For square type CNT bundles as shown in Fig. 1(a), the number of CNTs along the
width is nW and number of CNTs along the height is nH. The total number of CNTs,
nSB is given by
Hence, the width wB and height hB of the bundle is given as
where, δ is the van der Vaal’s gap equal to 0.34nm. We consider the arrangement
of CNTs in columns rather than the one described previously [9] such that the
total number of CNTs in both square type as well as triangle type bundle is same,
thereby making the analysis easy and comparable.
For the triangular bundle as shown in Figure 1(b), considering the fact that the
number of CNTs along each row is odd, the total number of CNTs in the bundle
nTB is given as,
where, nS is the number of CNTs along the side and nB is the number of CNTs
along the base of the triangular bundle. So, for the sake of simplified analysis, we
consider nSB = nTB.
Equivalent Single Conductor Model of CNT interconnects: We consider
in this paper that all the CNTs in the bundle are metallic, instead of considering
only one third. This makes our analysis unique with respect to previous analyses
[5-7, 9]. The ESC resistance of a bundle with nTB = nSB conducting SWCNTs is given
by
y is distance between centre of CNTs facing the ground and dg is the
diameter of those CNTs.
Fig. 2. ESC model of CNT bundle interconnects Fig. 3. Driver-interconnect-load (DIL) setup
The electrostatic capacitance between the ground and the interconnect will
change as the number of CNTs facing the ground varies for both the type of
bundle interconnects.
Transient Analysis: We use a driver-interconnect-load (DIL) setup as shown in
Fig. 3 to perform transient analysis. We consider the ASU Predictive Technology
Model (PTM) library [18] based inverter as driver at 20nm technology node.
(a) (b)
Fig. 4. (a) Propagation delay of square type and triangle type bundled CNT
interconnects, (b) Transient analysis output voltage of square and triangle type
bundles at different interconnect lengths of 500, 1000, 1500 and 2000µm.
Crosstalk in coupled interconnects:
Fig. 5. Coupled CNT bundle interconnects.
(a) (b)
Fig. 6. Coupling capacitance at various lengths and number of CNTs in bundle. (a)
Square bundle, (b) Triangle bundle.
Fig. 7. Schematic of capacitively coupled interconnects
Fig. 8. Delay improvement of triangle interconnects
over square interconnects for various no. of CNTs in
a bundle and at various lengths
Conclusions: We had studied the influence of geometry on the crosstalk
induced delay in coupled Carbon nanotube bundle interconnects. We found that
for triangle cross sectioned CNT bundle interconnects, the coupling capacitance is
29% lesser than square cross sectioned CNT bundle interconnects. Further, using
SmartSPICE software, we had carried out simulations of MESC models of
interconnects using a DIL setup. We found that the crosstalk induced delay is 30%
less for a triangle type bundle compared to square type bundles at lengths of 500,
1000, 1500 and 2000µm.
Introduction: Performance and reliability of future VLSI circuits is a major issue
in electronics industry [1]. Metallic CNTs, were modelled as transmission lines
(TLs) that can carry high frequency electric signals (>1GHz) between transistors in
an IC [5-7]. Recent work shows that adjacent interconnects suffer from crosstalk
especially during out of phase transitions of the input signals [9-11]. This crosstalk
induces a capacitive delay characterized by a coupling capacitance. In long global
interconnects whose lengths range from 500µm to tens of millimeters, this
capacitive coupling will be very high and is a major factor that contributes to the
propagation delay of wires [9]. For copper interconnects, this capacitive coupling
was reduced by using multiple dielectric materials as the cladding and etch stop
layers, as well as by separating adjacent wires by a safer distance. However, as the
technology progresses to nanometer scale, using of large separations by multiple
dielectrics is becoming a less feasible option. We propose a novel triangle shaped
bundle geometry of CNT bundle interconnects such that the crosstalk induced
delay of coupled interconnects is minimum. The dynamic crosstalk behaviour of
the interconnects at in-phase and out-of-phase scenarios by considering them as
capacitively coupled interconnects placed on a grounded substrate and by
modelling them using a driver-interconnect-load (DIL) setup.