Digital to analog -Sqaure waveform generator in VHDL
1. Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity square_wave is
Port ( clk_m : in STD_LOGIC;
rst : in STD_LOGIC;
clk_d : inout STD_LOGIC;
square_out : out STD_LOGIC_vector(7 downto 0));
end square_wave;
architecture Behavioral of square_wave is
signal scale: std_logic_vector(30 downto 0);
signal temp: std_logic_vector(7 downto 0);
begin
clk_d<=scale(26);
process(clk_m,rst)
begin
if rst='1' then
scale<= (others =>'0');
elsif clk_m'event and clk_m='1' then
scale <= scale + 1;
end if ;
end process;
2. process(clk_d,rst)
begin
if rst='1' then
temp<=(others=>'0');
elsif clk_d'event and clk_d='1' then
temp<=not temp;
end if;
end process;
square_out<=temp;
end Behavioral;
TEST BENCH CODE FOR SQUARE WAVE:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_vhd IS
END tb_vhd;
ARCHITECTURE behavior OF tb_vhd IS
COMPONENT square_wave
PORT(
clk_m : IN std_logic;
rst : IN std_logic;
clk_d : INOUT std_logic;
3. square_out : OUT std_logic_vector(7 downto 0));
END COMPONENT;
SIGNAL clk_m : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL clk_d : std_logic;
SIGNAL square_out : std_logic_vector(7 downto 0);
BEGIN
uut: square_wave PORT MAP(
clk_m => clk_m,
rst => rst,
clk_d => clk_d,
square_out => square_out);
PROCESS
BEGIN
rst<='1';
wait for 10 ns;
rst<='0';
wait; -- will wait forever
END PROCESS;
PROCESS
BEGIN
clk_m<='1';
wait for 10 ns;
clk_m<='0';
wait for 10 ns; -- will wait forever
END PROCESS;
END;