2. : Sequential Circuits :
• Sequential Circuits are those whose outputs are also dependent upon
past inputs, and hence outputs.
• In other words, the output of the sequential circuits may depend upon its
previous outputs.
• The two most popular varieties of storage cells used to build sequential
circuits are:
• Latches.
• Flip-Flop.
3. : Latches :
• Latches are the building blocks of sequential circuits and these can be built
from logical gates.
• It is a level sensitive storage element.
• Latch does not have a clock signal.
• Some examples of latches are:
• SR Latch.
• S'R' Latch.
• D Latch (gated D latch).
4. :SR Latch: :S'R' Latch:
• The simple bi-stable device is called SR
Latch.
• To create an SR Latch, we can wire two
NOR gates in such a way that the output of
one feeds back to the input of another,
and vice versa, like this:
• "Cross- coupling" two NAND gates gives
the S'R' Latch.
• Which has the time sequence behavior.
• S=0, R=0 is forbidden as input pattern.
5. : D Latch (Gated Latch) :
• The name "data type latch" refers to a D-type flip-flop that is level-
triggered, as the data (1 or 0) appearing at D can be held or 'latched' at
any time whilst the Clk input is at a high level (logic 1).
• For the D Latch, Q+ represents the state of flip-flop a short time after the
active clock-edge.
6. : Flip-Flop :
• Flip-flop are also the building blocks of sequential circuits.
• But, these can be built from the latches.
• It works on the basis of clock pulses.
• They are used as a registers.
• Flip flops are edge-triggered.
• Flip flop is sensitive to a signal change.They can transfer only at single
instant, and data cannot be changed until next signal change.
7. : Edge-Triggered Flip-Flop :
• An edge-triggered flip-flop changes states either at the positive edge
(rising edge) or at the negative edge (falling edge) of the clock pulse out
the control input.
• A rising edge-triggered flip-flop can be constructed from two gated D
latches and an inverter.
• These flip-flop are very useful, as they form for shift registers, which are
an essential part of many electronic devices.
8. : Flip-Flop with Additional Inputs :
• Flip-flops often have additional inputs which can be used to set the flip-flop to an initial state
independent of the clock.
• When designing a synchronous system, we frequently encounter situations when we want
some flip-flops to hold existing data even if the data input may be changing.
• There are two approaches:
• Gating the clock = may results in the loss of synchronization.
• A Flip-flop with clock enable = cost extra power.
• Flip-flop with clear and present inputs :
• A logic 0 applied to ClrN will reset Q to 0.
• A logic 0 applied to PreN will set Q to 1.
• ClrN and PreN are often referred to as asynchronous clear and present inputs.
9. : Asynchronous Sequential Circuits :
• Asynchronous inputs on a flip-flop have control over the outputs (Q and
Not-Q) regardless of clock input status.
• These inputs are called preset (PRE) and clear (CLR).
• The preset input drives the flip-flop to a set state while the clear input
drives it to a reset state.
• It is possible to drive the outputs of a J-K flip-flop to an invalid condition
using the asynchronous inputs, because all feedback within the
multivibrator circuit is overridden.
