The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme. The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.

1. Counter and Sequencer Design Digital Logic and Software Principles © University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License .

3. Counters There are two design methodologies, these being: Asynchronous Design Synchronous Design The choice of method will depend upon a number of factors including: Speed at which the counter is to operate Ease of design We will look at both methods. Counter & Sequence Design

4. Asynchronous Design If we have a JK bistable and the J and K inputs are set at logic 1 then it will act as a toggle bistable. If we have a number of these in a line then we will have the following: We will assume the bistables are falling edge triggered. The timing diagram on the next slide shows how the Q outputs vary as the clock is pulsed. J K Q Q Ck J K Q Q Ck J K Q Q Ck 1 1 1 1 1 1 Clock Q A Q B Q C

5. clock Q A Q B Q C         1 0 1 * Note that this acts as a counter – after the 5 th pulse on the clock the outputs read 1 0 1 (Q C , Q B , Q A ). This type of counter can suffer from a delay in the reading being correct – let us look in detail at the change marked with an asterisk .

6. The timing diagram shows an expanded version of the previous diagram around the moment marked with an asterisk. t is the delay through a single JK bistable. In total we have a possible delay of 3t With an “n” bit counter we could have a maximum delay before the count is correct of nt. This may be a problem with fast counters. clock Q A Q B Q C t t t

7. Assuming that the delay is not a problem we can simply extend the number of bits in the counter by adding more JK bistables. To count up to 15 we would need 4 bistables To count up to 255 we would need 8 bistables To count up to 1023 we would need 10 bistables To count up to 65535 we would need 16 bistables If the count needs to stop at a certain value and return to zero (e.g. a decade counter … 0  9 then back to 0) then this can achieved by recognising the next number and immediately resetting the bistables to 0. Counter & Sequence Design

8. Decade Counter. The normal 4 bit counter is converted in the following way The NAND recognises 1010 (10) and resets Q D Clock Q A J K Q Q Ck 1 1 Cl Pr 1 Q B J K Q Q Ck 1 1 Cl Pr 1 Q C J K Q Q Ck 1 1 Cl Pr 1 J K Q Q Ck 1 1 Cl Pr 1 1 1 1 1

9. It is possible to have quite complex count sequences: 1 1 1 1 Counter & Sequence Design Q D Clock Q A J K Q Q Ck 1 1 Cl Pr Q B J K Q Q Ck 1 1 Cl Pr Q C J K Q Q Ck 1 1 Cl Pr J K Q Q Ck 1 1 Cl Pr

10. The count sequence is as follows: Assume count starts at 0000 Count rises until we hit 0111 (7) – the right NAND recognises this. Q A and Q C are reset and Q D is set – 1010 (10) Count now continues until we hit 1101 (13) – the left NAND recognises this. Q C and Q D are reset – 0001 (1) The sequence is therefore: 0 – 1 – 2 – 4 – 5 – 6 – 10 – 11 – 12 – 1 – 2 – 3 - etc Counter & Sequence Design

11. The design of asynchronous sequencers is not ideal as we must momentarily hit the number that will trigger the jump. This means that for a short time a number appears on the outputs which should not be there – in our previous example 0111 (7) and 1101 (13). This may lead to false triggering of other parts of the logic circuit. Synchronous design does away with this problem as the sequence is designed into the circuit. It also does away with the problem of delays as all bistable change at the same moment in time. Counter & Sequence Design

12. Synchronous Design Before we look at the design methodology, we need to look back at the operation of the JK bistable. If we know the current state of the bistables output and we know what we wish it to be after the clock, we can use the table to determine what J and K need to equal. There are four possible “before and after the clock” conditions. Counter & Sequence Design J K Qn+1 0 0 Qn 0 1 0 1 0 1 1 1 Qn

13. Consider the situation where Qn = 0 and after the clock pulse we want it to stay at 0 i.e. Qn+1 = 0 What must J and K equal for this to be the situation? Either of these would give the desired effect. Combining these we can say: As long as What about the rest? Counter & Sequence Design

14. Consider the situation where Qn = 0 and after the clock pulse we want it to change to 1 i.e. Qn+1 = 1 Combining these we can say: As long as Consider the situation where Qn = 1 and after the clock pulse we want it to change to 0 i.e. Qn+1 = 0 Combining these we can say: As long as Counter & Sequence Design

15. Consider the situation where Qn = 1 and after the clock pulse we want it to stay at 1 i.e. Qn+1 = 1 Combining these we can say: As long as Summarising this gives us: We can now use this to design a synchronous counter or sequencer. Counter & Sequence Design Qn Qn+1 J K 0 0 0 1 1 0 1 1

16. Design sequence – fill in the table - 3 bit binary counter Counter & Sequence Design Present State Next State A B C A B C A B C J K J K J K

18. C K – This can be realised using C J - This can be realised using B K - This can be realised using B J - This can be realised using A K - This can be realised using A J - This can be realised using Counter & Sequence Design A C B 0 0 0 1 1 1 1 0 0 1 A C B 0 0 0 1 1 1 1 0 0 1

19. We can now construct the logic diagram for the counter. Note the clock goes to each bistable. The Cl and Pr are not required but must be connected to logic 1. This counter is more complex to design but the correct count number is reached in 1t – this is true for any number of JK bistables in the counter Clock C J K Q Q Ck B J K Q Q Ck A J K Q Q Ck

20. Design a counter which counts from 1 to 5 then back to 1 i.e. 001  010  011  100  101  001  010 etc Counter & Sequence Design Present State Next State A B C A B C A B C J K J K J K

21. C K – This can be realised using C J - This can be realised using B K - This can be realised using B J - This can be realised using A K - This can be realised using A J - This can be realised using If there are spaces in the Karnaugh map fill them with X’s Counter & Sequence Design A C B 0 0 0 1 1 1 1 0 0 1

22. You will note that only five out of the possible eight combinations of Q A , Q B and Q C have been used. It is important to know what happens if the system starts in one of the three which are unused. Counter & Sequence Design Clock C J K Q Q Ck B J K Q Q Ck A J K Q Q Ck

23. We can see that 000 (0) goes to 110 (6) goes to 111 (7) goes to Counter & Sequence Design Present State A B C Next State A B C J K J K J K A B C

24. We can now draw the State Diagram Counter & Sequence Design

25. Design a sequencer with the following sequence built in. i.e. 011  111  010  101  000  011  111 etc Counter & Sequence Design Present State Next State A B C A B C A B C J K J K J K

26. C K – This can be realised using C J - This can be realised using B K - This can be realised using B J - This can be realised using A K - This can be realised using A J - This can be realised using We have a number of options as to what to use for the J and K inputs – we will select the first one in each line. Once again we only use five out of the possible eight combinations of QA, QB and QC. It is good practice to check the solution. Counter & Sequence Design

27. We can see that 001 (1) goes to 100 (4) goes to 110 (6) goes to Counter & Sequence Design Present State A B C Next State A B C J K J K J K A B C

28. We can now draw the State Diagram Counter & Sequence Design

30. We can see that 001 (1) goes to 100 (4) goes to 110 (6) goes to New combination is fine. Counter & Sequence Design Present State A B C Next State A B C J K J K J K A B C

31. We can now draw the State Diagram Now we can look at the logic diagram. Counter & Sequence Design

32. Design a sequencer which will follow the sequence of a set of UK traffic lights. Counter & Sequence Design Clock C J K Q Q Ck B J K Q Q Ck A J K Q Q Ck

33. Counter & Sequence Design This resource was created by the University of Wales Newport and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. © 2009 University of Wales Newport This work is licensed under a Creative Commons Attribution 2.0 License . The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence. All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher. The name and logo of University of Wales Newport is a trade mark and all rights in it are reserved. The name and logo should not be reproduced without the express authorisation of the University.