The 8086 microprocessor uses a pipelined architecture with two independent functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handles data/address transfers between memory/I/O devices and the processor. The EU receives instructions from the queue, decodes them, and executes them. While the EU is decoding/executing an instruction, the BIU fetches the next instruction, allowing the two units to operate in parallel for improved performance over non-pipelined processors like the 8085. The 8086 can address registers as either 8-bit or 16-bit and uses segment registers to address 1MB of segmented memory space.

1. MICROPROCESSOR 8086
LECTURE 32
8086 MICROPROCESSOR PIPELINED ARCHITECTURE
PROF. SANDIP DAS

2. ARCHITECTURE OF 8086-INTRODUCTION
• 8086 Contains two independent
functional units: Bus Interface Unit (BIU)
and Execution Unit (EU)
• The BIU handles transfer of data and
addresses between the processor and
memory I/O devices.
• The EU receives opcode of an
instrument from the queue, decodes it
and then executes it.
• While EU is decoding an instruction or
executing an instruction, the BIU
fetches instruction codes from the
memory and stores them in the queue.
• The BIU and EU thus operate in parallel
independently and this type of
BIU
EU
MEMORY

3. PIPELINING IN 8086
Non-pipelined 8085
Pipelined 8086
Fetch 1 Execute 1 Fetch 2 Execute 2
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
T1 T2 T3 T4
T1 T2 T3 T4

4. ARCHITECTURE OF
8086
The Execution
Unit executes
instructions for
the processor

5. ARCHITECTURE OF
8086
Can be
addressed
either as 8 bit
register or 16
bit register
When
addressed as
8-bit register
AL-
Accumulator
low
AH-
Accumulator
High
When
addressed as
16-bit register
AX
BX
CX
DX

6. ARCHITECTURE OF
8086
Segment registers are used
to address memory space-
either RAM,ROM or the I/O
space
The address compute
engine converts the logical
address that is held by the
segment registers into
physical address
Internal memory holds the
Instruction queue

7. BUS INTERFACE UNIT
CODE SEGMENT
EXTRA SEGMENT
STACK SEGMENT
DATA SEGMENT
1 MB
SEGMENTED
MEMORY