please find my resume

1. NAYANA BU
Mobile No. : 9353040649,9741187497
E-mail : nayana.elec@gmail.com
Linkedin: https://www.linkedin.com/in/nayana-bu-8bb79714a
CAREER OBJECTIVE
To work in an organization where I can use my skills and knowledge to deliver value added results as well as further
enhance my learning and develop my career in the field of VLSI industry.
AREA OF INTERESTS
◦ RTL design
◦ Physical design
◦ Static Timing Analysis
◦ Digital circuit design
◦ Layout design
EDUCATIONAL QUALIFICATION
2019 - 2021(Pursuing)
Master of Technology in VLSI Design and Embedded
systems
MS Ramaiah instituteof technology, Bangalore
CGPA:8.4
2015 - 2019
Bachelor of Engineering in Electrical and Electronics
Engineering
The Oxford college of engineering, Bangalore, Karnataka
CGPA:7.4
2013 - 2015
PUC
Vidyavahini PU college, Tumkur, Karnataka
Percentage:85.33%
2012 - 2013
SSLC
GJC, Gubbi, Karnataka
Percentage:80.41%
ACADEMIC PROJECTS
M.TECH 1
TITLE: High bandwidth multi-modulus clock divider (2020-2021).
TOOL : Cadence-Virtuoso using gpdk45 technology
DESCRIPTION: This project involves the implementation of multi modulus divider used in High speed SerDes
application which does division of 10G Hz input clock at 1V with different division numbers
ranging from 2 to 255.Designed most of the standard cells which include NAND, NOR, MUX, and
Sequential blocks using gpdk45nm in cadence virtuoso to meet speed ,power and area.
Implemented the layout of fundamental cells used in the design using cadence layout editor and
design is validated for Layout vs Schematic Check(LVS) as well as Design Rule Check(DRC),
Extraction of layout is done using Cadence PVS extraction to annotate the RC impact for post
layout circuit simulations.
M.TECH 2
TITLE: Design of Approximate Hybrid High Radix Encoding for energy efficient multipliers (2019-2020).
TOOL: Xilinx vivado.
DESCRIPTION: This project involves the design of a power and area efficient multiplier using different
methodology. Designed using Verilog and simulated the design using Xilinx vivado and Results
shows that designed multiplier accuracy increases as we go for higher bits multiplication and it
is power and area efficient.

2. BE
TITLE: Power quality improvement by using STATCOM control scheme in wind energy generation
interface to grid (2018-19).
TOOL: MATLAB
DESCRIPTION: The STATCOM control scheme for the grid connected wind energy generation system for power
quality improvement is simulated using MATLAB in power system block set. The effectiveness of
the proposed scheme relives the main supply source from the reactive power demand of the
load and the induction generator.
INDUSTRIAL EXPERIENCE
◦ Completed my Internship in Karnataka Vidyuth Karkhane Pvt ltd. Duration from 6th
July 2018 to 4th
August2018
◦ Completed my Internship in SK high voltage equipment’s . Duration from 15th
January 2018 to 31 January2018
ACHIEVEMENTS
◦ Represented VTU in all India Inter-University Kabaddi (Women) team-2018.
TECHNICAL SKILLS
◦ Hands On experience in Verilog.
◦ Hands On experience in Xilinx vivdo.
◦ Cadence Virtuoso ADE XL for Schematic and ADE Layout XL for Layout Design, Simulation and Debugging.
◦ Cadence PVS Extraction.
COURSE’S AND CERTIFICATION’S
◦ Completed course on ‘VSD-Static TimingAnalysis’ Part-1 and Part-2 in Udemy.
EXTRA CURRICULAR ACTIVITIES
◦ Active volunteer in WayForLife(NGO).
◦ Soft-Skill Trainer in Team Spoorthi .
PERSONAL DETAILS
◦ Date of Birth : 03 Nov 1997
◦ Address: No#416 Bhadrapura, Tiptur||Tq||, Tumkur||Dist||-572114.
◦ Father’s Name : Umesh BM
◦ Mother’s Name : K S Chandrakala
DECLARATION
I hereby declare that all the information above are true to the best of my knowledge. References will be furnished as
and when required.
NAYANA BU
Bangalore