1. Kukkam Narasimha Reddy
M.Tech, Microelectronics and VLSI
IIT Roorkee
Email: narasimhareddy.422@gmail.com Mobile No: 8792238872
Objective: To be a part of an organization where my acquired skills help in company’s growth
and in building up a strong career in my field of interest by acquiring knowledge through
challenges.
Experience: (2 Year 8 Months) on compiler/custom memories, Pulse width modulator, and
clock spine for Microprocessor.
Nov 2013 – August 2015 (1 year 10 months) -AMD
August2015 –Till Now (10 months) -SYNOPSYS
Project (current): Compiler memories which are building block for microprocessor. I have
worked on different technologies such as 14LPP, 16FFP, 20LPM and 28HPC for leading
foundries.
Key Roles:
 Design analysis of different architectures to finalize the best fit in order to meet the
design targets.
 For a novel architecture, development of Placement files that is used for initial functional
and circuit checks also for final GDS generation, Timing, Power and Leakage
characterization.
 Design changes to meet timing margins, leakage, power correlation and noise reduction.
 Root Cause and corrective Action analysis for keeping the timing numbers close to
estimated Front End numbers by taking care in layout as well as design.
 Debugging and fixing the trend issues, development of schematics and scripts.
Spot Recognition award from AMD, for the effort in release of macros using IPCR.
Key Roles:
 Experience with circuit techniques like power gating, clock gating, Characterization of
Critical paths, race conditions, STA and .lib generation
 Knowledge of EM, IR drop, SNM, Cell current, Standby current.
 Creation of Verilog Front-end Views including behavioral, power, ATPG, ESPSHELL
and LEC
 Noise, EMIR, Totem flows, Statistical tolerance analysis (Monte-Carlo)
Skills acquired:
 EDA tools like schematic editors, circuit simulators, scripting languages, waveform viewers,
internal tools, flow for Circuit and Memory Characterization
 Ready to take responsibility and go the extra mile to accomplish tasks on time, learn and grow
Educational Qualifications:
• Post Graduation: M.tech in Microelectronics and VLSI
IIT Roorkee, 2013 CGPA: 7.863
• Graduation: Electronics & Instrumentation in
Aurora Engineering College, Bhongir, 2010 68.68%
• Intermediate: Board of Intermediate Education, A.P, 2005 90.20%
• High School: S.S.C board, A.P, 2003 89.50%

2. PROJECTS
Performance analysis of Multi-layer Graphene nanoribbon interconnects
Shrinking in technology also moving to FINFETs also reduction in chip area current density in
interconnects is increased drastically which is causing Electromigration (signalEM and powerEM) and
IR effects. In lower technologies because of lower W/H ratio conductivity becomes less, in order to
overcome all these effects in Microprocessor traditional Aluminum and Cu Interconnects are going
obsolete. For the next generation processors urgently require Interconnects that are able to carry large
current density. The solution lies with Graphene derivatives. Graphene Nanoribbons being one of them
can support large current density at high frequencies. My project is Cross Talk analysis in MLGNR
interconnects and Modeling of delay with respect to process variation and temperature variation.
Elective Courses in M.tech: Digital VLSI design, Analog VLSI circuit Design.
Academic Awards / Achievements:
I) “Delay uncertainty in MLGNR interconnects under process induced
variations of width, doping, dielectric thickness and mean free path” Journal
of Computational Electronics, Springer
II) “Frequency response and bandwidth analysis of multi-layer graphene
nanoribbon and multi-walled carbon nanotube interconnects” IEEE journal
in Micro & Nano Letters, IET
III) GATE AIR 214.
Participation in Extra-Curricular Activities:
COGNIZANCE (2012)
Worked as coordinator for E&C Departmental paper presentation during
COGNIZANCE-2012 held at IIT Roorkee
TARANGINI (2012)
Worked as TOC (Tarangini organizing committee) member during Tarangini-2012 held
at IIT Roorkee.
TARANGINI (2012)
Winner of foosball held During Tarangini-2012 at IIT Roorkee
PERSONAL DETAILS:
Address: Email id:narasimhareddy.422@gmail.com
S/o: K. Chenchu Reddy, Mobile: +91 8792238872
Vemula (Village), DOB: 14th April 1989
Itikyala (Mandal) References to be provided on request
Mahabub Nagar (Dist),
Andhra Pradesh- 509128