Nagendra Addagarla

Greater San Diego Area United States

Design Verification Engineer at Qualcomm

Electronics / Computer Hardware

Design and Verification Engineer with 9+ Years of experience Specialties: Functional Verification using System Verilog and OVM/UVM methodologies including the design of coverage driven and constrained random test benches. Experience in test planning, debug, SOC and block level verification. Planning for code coverage and functional coverage metrics. Experience with UPF power aware simulations and debug. Experience in the use of formal verification techniques like system verilog assertions and equivalence checking. Thorough with the concepts of CDC clock domain crossing, DFT - Design for testability, STA static timing analysis and ASIC design flow.