1. Michael M. Young
Diamond Bar, CA 91765
(909) 569-3283(cellphone); Email: myoung72799@gmail.com
(For italics text, please refer to glossary)
Objective: Seeking a principal/staff level electronic/hardware engineering, or system architect, or engineering
management position, in Southern California area, San Diego not included.
Experience
Highlights:
More than 25 years of experience in system/hardware board design, from design specification to
product delivery, leading small groups of people. In depth knowledge in digital and analog
electronics, programmable devices and programming languages, personal computer architects and
designs, digital data processing, video image technology, interface standards (VME, PCI, PCI-X,
PCI-Express, PMC, AGP, FPDP, Serial FPDP, Ethernet, Rapid IO, Serial ATA, DVI, IEEE 1394,
USB, NTDS protocol…), A/D and D/A conversions, power regulations, high speed issues and
design, PCB designs, EMI issues and regulatory compliances.
Duties include defining and planning projects, leading design teams and managing schedule and
resources, solving technical problems, implementation, prototyping, debug, test, interface to the
customers, supporting upgrades and manufacturing.
Education: M.S.E.E., Aug. 1988, Texas Tech University, Lubbock, Texas.
B.S.E.E., May 1986, Texas Tech University, Lubbock, Texas.
Thesis Topic
and Project:
A Vision System for a Small Image Array. Designed and developed a PC based camera
driver/video digitizer system for a small-area CCD image sensor. The system employed software
signal processing techniques, hardware memory expansion and interface, A/D digitizing, digital
and analog circuitry. Digital circuits were implemented using Altera EPLD and TTL/CMOS
devices.
Employment:
(2014 to
2015)
Major Task:
SMART Modular. Irvine California (Headquartered in Newark, California).
SMART Modular designs and manufactures industrial grade, specialized DIMMs.
Principal Hardware Engineer/Product Architect.
StrataDIMM. StrataDIMM is a DDR4 NVDIMM type F design whose detail specification is still
being defined. My job was to lead a development team through the following stages, and deliver
the product successfully.
• Working with JEDEC and others in the same field to help define NVDIMM type F
specification,
• Define StrataDIMM features, specifications and architecture, including DDR4 slave front
end interface, DDR4 on-board cache, Toggle 2 Flash memory, 10G Ethernet, power
consideration, physical form factor.
• IP selection, evaluation, and development. Define NVDIMM type F slave controller
specification, select vendor to work with for IP development. Evaluate Flash controller IP,
Encryption IP, select vendor to work with on feature development. Evaluate and select
processor IP, 10 Gigabit Ethernet IP, DMA, interconnect, and miscellaneous IPs.
• FPGA selection and application, design hardware platforms, schematic capture, BOM.
• Thermal analysis, timing analysis, power analysis, SI analysis using Ansys SIwave.
• Manage overall project progress, communication with marketing, engineering, potential
customers, IP developers, vendors.
All aspects of development were progressing well. IPs, firmware, Flash Translation Layer, test
platforms, hardware were all being developed on schedule, when SMART Modular decided to
shut it down due to Company financial hardship.

2. (2012 to
2014)
Major Task:
(2010 to
2012)
QLogic. Aliso Viejo, California.
Qlogic specializes in networking communication products such as Fibre Channel and Ethernet.
Principal Hardware Engineer
I. Detroit, a PCIe 8"length/full height 16G FC adapter. Designed this product from product
requirement to prototype, using 2x QLogic FC/CNA controllers, with a PLX Gen3 PCIe switch, 8
lane PCIe interface, PCIe and external power supply, designed multiple power regulators and auto
power switching, designed for manufacturing, 14 layer PCB. Completed DVT and EVT tests.
Product in pilot production.
II. Ojai, a PCIe 6"length/full height 16G FC adapter. A modified version of Detroit with
smaller form factor, using 2x QLogic FC/CNA controllers, with a PLX Gen3 PCIe switch, 8 lane
PCIe interface, and single power source from edge connector, designed multiple power regulators,
designed for manufacturing, 10 layer PCB. Completed DVT and EVT tests. Product in pilot
production.
III. Customer design review. Reviewed customer designs that use QLogic controller ASICs.
Corrected errors, suggested improvements, answered questions.
IV. Engineering design process. Reviewed and helped establishing design process, from
specification, to design checking milestones, to documentation, to EVT and DVT.
STEC. Santa Ana, California.
STEC designs and productizes SSD. The Company was brought out in 2013.
Sr. Staff Hardware Engineer
Major Task: I. PCIe half length/half height single board drive. Designed this product from product
requirement to prototype, using Nozomi. The drive has a 4-lane PCIe interface, supports up to
1TB of flash memory and 2GB of DDR3 memory. Design included power regulations and thermal
simulation and solutions. Complete EVT test.
II. Thermal Simulation. Using SolidWork’s FlowSimulation to simulate heat signatures for PCIe
cards, 1.8”, 2.5” chassis and 3.5” chassis for various SATA, SAS, FC products. Provided
recommendation for chassis and heatsink designs.
(2007 to
2010)
Adaptec STP Division. Foothill Ranch, California.
Built FPGA-based board to emulate the new ASIC design, built reference design board to test new
ASIC, solved technical issues, and supported current ASIC already in customer design. STP
division was closed down in 2010.
Sr. Staff Hardware Engineer
Major Task: I. Product support. Support products using the 3rd
generation RAID controller, AL3450 device.
Supports included design analysis and review, board tests and debugs, documentation.
II. NEP Hardware Support and ASIC Emulation. NEP is a hardware platform with 10 large
Xilinx Virtex IV FPGAs(LX200, FX140, and FX20), and also PCIe, SAS/STAT, Ethernet and
various interfaces. ASIC code is broken down into 10 difference pieces and programmed in these
FPGAs. Simulations are run to test the codes. My duties are supporting the platform hardware,
programming and analyzing code sizes, timings, errors. Corrective actions are taken to ensure the
codes are properly programmed and functioned.
III. NVB Hardware Verification Platform. NVB is a hardware platform that verifies the
NanoSlice silicon. The board is on a full size PCI form factor, with a PCIe II interface, DDR3
interface, an internal and an external 6G SAS/STAT, Gigabit Ethernet and various other interfaces.
The board also includes various mechanism for tests and measurements. Board was completed and
is used for ASIC verification .
(2002 to
2007)
Micro Memory. Chatsworth, California.
Designs and productizes active disc electronic storage systems for data applications and backups.

3. The company no longer exists.
Staff Hardware Engineer
Major Task: I. Mother board active disc(MM-7460). A computer motherboard with a Motorola Power
PC(MPC8245), supports up to 64GByte SDRAM memory, 4 PCI 66MHz slots, 1 PMC slot, 1
Gigabit Ethernet(82545EM) link, and 2x SATA(88SX5080) hard drives. Hardware included 3
PCI-X bridges(PLX6540), 2 PCI Memory controllers with DMA, and 2x600W redundant power
supplies.
II. PCI-X board with 1Gbyte memory and 24 SATA channels(MM-5429). A full length, full
height PCI-X card supported up to 1Gbyte of SDRAM memory with battery back up to 72 hours.
Hardware included 3 SATA controllers(88SX5081), 3 PCI-X bridges(31154), with power circuit to
provide power.
III. PMC board with dual serial FPDP agents(MM-6137FC). A PMC board with 2 serial
FPDP interface channels. Each channel has a maximum full duplex speed at 247MByte/s, and the
combined 2 channels supported 460MByte/s. Implementation used Systran’s PMC/SFPDP
chipsets, 20bit serial/deserializers, and ZBT memory as receiving FIFOs. Major internal buses
were running at 125MHz and serial optical fibers at 2.5GHz.
(1996 to
2002 )
Anigma Inc. Diamond Bar, California.
Anigma was primarily a PC motherboard design house.
Sr. Hardware Engineer
Major Task: I. HP server motherboard. A dual Slot1 system with Reliance Computer Corp’s chipset.
133MHz front-side bus, 8GB memory, VGA graphic and AGP slot, 33MHz Primary and 66MHz
secondary PCI slots, Intel 10/100TX LAN device, Crystal Audio controller and MIDI port, HDD,
Floppy, USB ports, serial, parallel ports, PS/2 keyboard/mouse, modified ATX form factor, 8-
layer PCB, double side component.
II. Gateway PC production motherboard. A Celeron processor with Intel BX/ZX chipset.
100MHz front-side bus, 512MB memory, 3DFX Banshee graphic controller with 8MB graphic
memory, Ensoniq Audio controller, AGP/PCI/ISA slots, HDD, Floppy, USB ports, serial, parallel
ports, PS/2 keyboard/mouse, micro ATX form factor, 4-layer PCB, single side component.
The project included two other variations. One motherboard used an older 3DFX graphic
controller with less graphic memory, and the other used an AMD’s K6 processor. There were a
total of 3 designs.
III. A LCD plug-in card for Gateway PC production motherboard. A plug-in card for flat
panel display. 3DFX xLCD controller, Silicon Image SIL150 transmitter, an Anigma defined 40-
pin connector for Gateway motherboard interface, 4-layer PCB, single side component.
IV. Intel reference motherboard. A slot1 processor with Intel BX chipset. 100MHz front-side
bus, 512MB memory, ATI graphic controller with 4MB graphic memory, ATI video encoder,
Yamaha Audio controller, AGP/PCI/ISA slots, HDD, Floppy, USB ports, serial, parallel ports,
PS/2 keyboard/mouse, ATX form factor, 4-layer PCB, single side component.
V. VMIC production motherboard. A Pentium class motherboard with Intel TX chipset.
66MHz front-side bus, external L2 Cache memory, one DIMM memory socket, Cirrus Logic
Graphic controller with 2MB graphic memory, DEC 10/100TX LAN device, HDD, Floppy, USB
ports, serial, parallel ports, PS/2 keyboard/mouse, PMC expansion connector, PCI/VME bridge
connector, VME connectors for power only, VME 6U form factor, 8-layer PCB, double side
component.
VI. OPTi reference motherboard. A Pentium class motherboard with OPTi’s single PC chipset.
66MHz front-side bus, external L2 Cache memory, SIMM and DIMM memory modules, RTC,
PCI and ISA buses, USB, serial, parallel ports, keyboard/mouse, ATX form factor, single side
component.
VII. Toshiba set top computer. An entertainment set top box featuring DVD for consumer
market. The system was a Pentium class PC with Toshiba chipset. 66MHz front-side bus, external

4. L2 Cache memory supports up to 16MB memory, Chromatic Research Mpact-1 system for
multimedia (3-D, 2-D graphics, AC-3 stereo audio, and modem), Analog Device video encoder for
NTSC Composite and S-video signal outputs, TI IEEE 1394 controller, HDD, USB ports,
PCMCIA, PS/2 keyboard/mouse. Toshiba specified form factor(approximately 6x9 inches), 8-
layer PCB, double side component.
(1993 to
1996)
Sabtech Industries. Anaheim, California.
Sabtech specialized in offering hardware and software products for the NTDS market.
Sr. Hardware Engineer
Major Task: I. NTDS/PCI product line. A new product line using modularized design approach implemented
in VHDL code. Each NTDS board had its own NTDS Type input/output VHDL modules while all
other modules were common in the product line. PCI interface was implemented with a PLX
bridge.
I led all development aspects of this product line, specifications, architecture and defined
functional blocks, supported VHDL coding, designed hardware implementation.
The project was a great success. Sabtech continued to develop products based on these modules,
different NTDS types, mixed or/and multiple NTDS channels on one hardware platform, customed
NTDS…. These modules were also modified to develop other NTDS product lines. In addition,
this project also help setting up Sabtech engineering design and documentation processes.
II. NTDS/VME product line. A new product line for NTDS VME market. This was a
modularized design with one VME motherboard and different piggybacks to support different
NTDS Types. Four piggybacks were completed to support Type A, A/B, C, and E.
The motherboard featured a Motorola 68340 microprocessor with 2 DMA channels, 2 serial ports,
and 2 user timers, a Cypress VME controller and Cypress companion devices for full VME
interface features, a DRAM controller and 4MB memory with 3MB hiding option for A24
systems, 2 flesh memories (one for the system bootup and one for the user), 2 FIFOs working with
DMA channels to increase the speed of data transfer, data swapping circuit to resolve differences
between Intel and Motorola data structure, VME P2 NTDS access, motherboard/piggyback data
multiplexing and demultiplexing, NTDS passive and active taps. The piggybacks supported full
NTDS interfaces, time tag, motherboard/piggyback data multiplexing and demultiplexing circuit.
Control logic written in ABEL codes and implemented in Atmel PLDs
III. NTDS/PC half size interface card. Modified the existing full size ISA version with an
improved design, surface mount technologies to build a half size ISA card for laptop and portable
PC market. Also fixed known bugs.
(1988 to 1993
)
Cymbolic Sciences International(CSI). Aliso Viejo, California.
CSI developed and manufactured Auto Optical Inspection Machines (AOI), Photo Plotters, and
other Imaging equipment.
Major Task: I. Multiple Image Line Detector. Project was designed to track lines of different width on a
PCB board. Implemented with Xilinx FPGA, PLDs, and TTL/CMOS.
II. Parallel and Serial Data Converter. Project was designed to convert data in parallel format
to serial stream, with data compression and expansion using CCITT Modified Huffman code,
implemented with TTL/CMOS logic and PALs.
III. Image Recognizer. The Board analyzed features on printed circuit boards based on
mathematics models and it triggered on features and/or flaws. Implemented with Xilinx FPGAs
and PALs and TTL/CMOS logic.
IV. Design of image grabber. Processed and digitized video signals for analysis, implemented
with TTL/CMOS logic and PALs.
(May 1986 to
May 1988)
Teaching Assistant, Electrical and Electronics Technology Dept., Texas Tech University, teaching
junior and senior level courses and labs, including lecture, lab projects, grading, tests, and
evaluation.

5. Design Tool: Ansys SIwave, SolidWork’s FlowSimulation, Xilinx ICE, Aldec, Lattice ispDesignEXPRRT,
ViewLogic schematic ProCapture, OrCAD/ESP design environment, Cadence Concept, P-Cad,
ABEL, AutoCad, Windows Office Suite.
Programmin
g Language:
VHDL, FORTRAN, BASIC, some C, and some Assembly Languages.
Test
Equipment:
Oscilloscope, logic analyzer, spectrum analyzer, multimeter, in-circuit-emulator (ICE).
License: EIT(Engineering in Training, prerequisite for PE exam), No. XE081556, California.
References: Available upon request.
Glossary
ABEL An integrated software environment for writing firmware for programmable devices.
AC-3 A Dolby stereo system that supports 6 individually coded channels, also known as Dolby Digital, Dolby 5.1.
ADC Analog to digital converter.
AFE Analog Front End.
AGP Advanced Graphic Port. An Intel defined high-speed bus standard for graphic application.
AOI Auto Optical Inspection Machines. These machines are used for PCB manufacturing quality control.
Altera EPLD An integrated system made by Altera Corp. to program the Altera programmable devices. Users might enter the design
in several ways; basic electronic circuit, logical equations, state machine diagrams.
ASIC Application specific IC.
ATX A computer mother board standard/form factor.
AutoCad A program that captures drawings with great dimensional accuracy favored by mechanical and architectural people.
BOM Bill of material.
Cache Cache memory is high-speed memory that holds the most recently executed instructions, in order to speed up the
processing time.
CCD Charged Coupled Device. These devices translate optical images into digital electronic representation. They are widely
used in Camcorders and digital camera.
CNA Converged network adapter.
DAC Digital to analog converter.
DDR Double data rate.
DIMM Dual-in-line memory module.
DMA Direct Memory Access. A way to access the memory in high speed.
DVD Digital Video Disc. Using MPEG2 compression scheme to store a large amount of information on an ordinary 5 1/4”
laser disc, usually enough for a full featured Hollywood film.
DVI Digital Visual Interface.
DVT Design verification test.
EMI Electro Magnetic Interference.
Ethernet IEEE 802.3 standard.
EVT Engineering verification test.
FC Fibre Channel.
FIFO First in first out memory.
FPDP Front Panel Data Port. A 40MHz, 32bit uni-directional parallel bus.
FPGA Field Programmable Gate Array.
Form factor Mechanical definitions of a PC board. Those definitions usually include dimensions, height restrictions, mounting hole
positions, etc.
GPS Global positioning system.
ICE In-circuit-emulator. Machines for microprocessor debugging.
IEEE 1394 Nicknamed “Firewire”, the IEEE 1394 is a high-speed serial interface that supports data rate up to 400Mbits/s with
possible future upgrades to 800Mbits/s. Mostly used in Camcorder video interface for now, the IEEE 1394 has other
potential applications such as digital camera, printer, hard disk.
IP Intel lecture property.
ISA Industry Standard Architecture. A bus standard for PC plug in modules.
iSCSI Inter Small Computer System Interface.
L2 cache External cache on PC mother board. L1 cache is internal cache in microprocessor.
LAN Local area network.
NTDS Naval Tactical Data System. Bi-directional protocols for data communication.

6. NVDIMM Non Volatile dual-in-line memory module.
OrCAD A hardware schematic design environment that includes schematic capture, simulation, simple PCB and PAL tool.
PC chipset A PC chip set is a group of chips (could be contained in one device) that support most or all the peripheral functions
outside of the main microprocessor. Examples of the peripheral functions are external cache, main memory, PCI, ISA,
harddisc, floppy, real-time clock, serial port interface, parallel port interface, USB, etc.
PCB Printed circuit board.
PCI Peripheral Component Interconnect. A bus standard for PC plug in modules.
PCI-Express A serial high-performance next generation I/O interconnect that maintains the key PCI attributes, such as usage model
and software interface.
PCI-X A follow-on PCI standard that supports 133MHz, 266MHz… with data rate of 1GBytes, 2GBytes…
PCMCIA Personal Computer Memory Card International Association. An interface standard that supports credit-size plug- in
modules.
PLD Programmable Logic Device.
PMC PCI mezzanine card.
RAID Redundant array of independent disks.
Rapid IO A Serial Link Protocol is a high-performance, low pin-count, and low-power serial packet-switched system level
interconnect open standard.
RTC Real Time Clock.
Reference motherboard A reference motherboard is an evaluation platform for a new chip/chip set.
SAS Serial attached SCSI
SATA Serial Asynchronous Transfer Attachment.
SAVII Secure audio video integrated interface.
SCSI Small computer system interface.
SDRAM Synchronous dynamic random access memory.
Serial ATA Serialized AT Attachment. A high speed serial link standard.
Serial FPDP The serial form of FPDP bus running at 2.5Gbit/s.
SIMM, DIMM DRAM base memory add-on modules.
S/PDIF Sony Philip digital interface.
SSD Solid state drive.
USB Universal serial bus. A median speed serial bus standard. Possible applications are keyboard, mouse, modem, audio.
VME A bus standard defined in late 70s for high data throughput systems, normally in industry environment.
VHDL Very high speed Hardware Description Language. VHDL is a portable, high level language for hardware design. The
code can be loaded into many different PLDs, FPGAs.
Xilinx ISE design suite An integrated system made by Xilinx to support designs on Xilinx FPGAs.
ZBT memory Zero bus turnaround memory. A type of memory that “look ahead” to achieve high speed data rate.

7. NVDIMM Non Volatile dual-in-line memory module.
OrCAD A hardware schematic design environment that includes schematic capture, simulation, simple PCB and PAL tool.
PC chipset A PC chip set is a group of chips (could be contained in one device) that support most or all the peripheral functions
outside of the main microprocessor. Examples of the peripheral functions are external cache, main memory, PCI, ISA,
harddisc, floppy, real-time clock, serial port interface, parallel port interface, USB, etc.
PCB Printed circuit board.
PCI Peripheral Component Interconnect. A bus standard for PC plug in modules.
PCI-Express A serial high-performance next generation I/O interconnect that maintains the key PCI attributes, such as usage model
and software interface.
PCI-X A follow-on PCI standard that supports 133MHz, 266MHz… with data rate of 1GBytes, 2GBytes…
PCMCIA Personal Computer Memory Card International Association. An interface standard that supports credit-size plug- in
modules.
PLD Programmable Logic Device.
PMC PCI mezzanine card.
RAID Redundant array of independent disks.
Rapid IO A Serial Link Protocol is a high-performance, low pin-count, and low-power serial packet-switched system level
interconnect open standard.
RTC Real Time Clock.
Reference motherboard A reference motherboard is an evaluation platform for a new chip/chip set.
SAS Serial attached SCSI
SATA Serial Asynchronous Transfer Attachment.
SAVII Secure audio video integrated interface.
SCSI Small computer system interface.
SDRAM Synchronous dynamic random access memory.
Serial ATA Serialized AT Attachment. A high speed serial link standard.
Serial FPDP The serial form of FPDP bus running at 2.5Gbit/s.
SIMM, DIMM DRAM base memory add-on modules.
S/PDIF Sony Philip digital interface.
SSD Solid state drive.
USB Universal serial bus. A median speed serial bus standard. Possible applications are keyboard, mouse, modem, audio.
VME A bus standard defined in late 70s for high data throughput systems, normally in industry environment.
VHDL Very high speed Hardware Description Language. VHDL is a portable, high level language for hardware design. The
code can be loaded into many different PLDs, FPGAs.
Xilinx ISE design suite An integrated system made by Xilinx to support designs on Xilinx FPGAs.
ZBT memory Zero bus turnaround memory. A type of memory that “look ahead” to achieve high speed data rate.