This document provides references for the digital IC layout and DFT consulting work of Michael Kogan. It summarizes his career experience in digital ASIC implementation since 1997, and lists the services he provides, including physical implementation, design for test solutions, technology conversions, and onsite/remote customer support. It then highlights several project examples and provides recommendations from customers praising Kogan's expertise, timeliness, and ability to complete complex projects on schedule. Contact details are provided at the end.

1. REFERENCE PROJECTS OF
MR. MICHAEL KOGAN
DIGITAL IC LAYOUT AND DFT
FREELANCER-CONSULTANT
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 1

2. 03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 2
INTRODUCTION

3. MR. MICHAEL KOGAN
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 3
 Career started in 1997, Freelancer since 2014
 Skill set span a unique wide range at all aspects of
Digital ASIC Implementation (RTL to GDSII ) flow, from RTL coding and
synthesis through Design for Test and Place & Route implementation to
Physical Verification and Tape-out to foundary
 Services:
 Physical Implementation of Digital IC: Synthesis, STA, Place and Route
 Design for test (DFT) solutions: scan insertion, hierarchical and low power DFT, test point
insertion, cell aware, stuck-at & at-speed ATPG etc.
 Spec to Packaged Chip: complete or partially outsourcing in cooperation with some design
houses
 FPGA design and implementation, include VHDL programming.
 Technology convertion: ASIC to ASIC, FPGA to FPGA, FPGA to ASIC etc...
 Team or individual ramp-up
 Methodology setup and optimization.
 Onsite or remote support

4. CUSTOMERS
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 4
 Support international customers in
EMEA and North America regions:
Germany, Great Britain, Serbia, Israel, USA
etc.
 Support customer from varios markets:
Consumer electronic, Telecomunication,
Automotive, Aerospace and Defence,
Health Care, etc.
References can be provided on demand

5. 03.05.2016
Reference Projects of Michael Kogan (michael.kogan@ic-link.eu) 5
PROJECT EXAMPLES

6. ADVANCED GPS/GALILEO ASIC
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 6
 RTL Synthesis to Hard Radiation Space dedicated Technology
 Static Timing Analysis (STA): Timing Constraints generation, multi
scenario STA
 Scan Insertion
 Stuck-at and at-Speed Automatic Test Pattern Generation
 Preparation for Layout: Floor plan, Clock Tree Synthesis
 Interface and teamwork with Layout Team on Physical Implementation
and Timing Closure.
Tasks
 Synopsis Design Compiler and Prime Time
 Mentor Tessent and Modelsim
 Defacto HIDFT-Signoff
 Cadence EDI
Technical Environment
The (Advanced GPS/GALILEO ASIC) is a radiation tolerant GNSS
baseband ASIC capable of processing the modernized GPS and
Galileo Signals. Due to its flexibility it is also able to process not
only GPS and Galileo but also other GNSS systems like Glonass,
Compass, etc.
Description
Client Reference :
EADS-Astrium , Germany

7. 4G LTE – WIRELESS COMMUNICATION PROCESSOR
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 7
 Scan Chain XOR compression
 Stuck-at and at-Speed Automatic Test Pattern Generation
 Fault coverage improvement
 Reduction of test vectors amount
 Test vector simulation
 Static Timing Analysis
Tasks
 Cadence RTL Compiler, Encounter Test, Ncsim
 Synopsys: Prime Time
Technical Environment
Description
Client Reference :
Altair Semiconductor, Israel
4G LTE – wireless communication processor chip to provide fast
and secure internet connection for modern mobile phone and
other commercial devices.

8. LAYOUT OF NETWORK PROZESSOR
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References Project of Michael Kogan (michael.kogan@ic-link.eu) 8
 Physical Implementation (Floorplan, Placement, Clock and Signal Routing,
Xtalk analysis and repair) of 3 sub-blocks, up to 3.5 Million instances each
 Timing closure
 Static Timing Analysis (STA)
 Power consumption at IRdrop reduction
 Physical Verification
Tasks
 Cadence EDI, Tempus, Voltus, PVS, Conformal-LEC
Technical Environment
Network Processor , 120 Mio. Instances, over 1.000 RAMS, average system
frequency over 500 MHz, Flip Chip package, 6 RC corners , 4 library sets,
multiple functional and test Timing Modes, 28nm TSMC technology. USA
based customer.
Description
Client Reference :
Cadence Design Systems, Germany

9. LAYOUT OF NETWORK CAMERA AND VIDEO SERVER PLATFORM DESIGN
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 9
 Physical Implementation of 3 sub-blocks, up to 3.5 Million instances each
 Timing closure
 Static Timing Analysis (STA)
 Power consumption at IRdrop reduction
 Physical Verification
Tasks
 Cadence EDI, Tempus, Voltus, PVS, Conformal-LEC, custom flow
management tools
Technical Environment
Description
Client Reference :
Renesas Electronic Europe, Germany
System-On-Chip (SOC) for networked surveillance
cameras Over 25Mio. gates, almost 450 Memories with
total 30Mbit , hierarchical physical implementation
with Cadence EDA tools at 28nm TSMC energy-efficient
and high-performance technology

10. IMPELENTATION OF HIGHLY PROGRAMMABLE
DIGITAL PROCESSOR
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 10
 Static Timing Analysis (STA): Timing Constraints generation, multi
scenario STA
 Scan Insertion
 Testability analysis and improvement atRTL
 Stuck-at and Delay-test Automatic Test Pattern Generation (ATPG)
 Support for layout team
Tasks
 Synopsis Design and DFT Compiler, Prime Time
 Mentor HDL-Designer, Tessent and Modelsim
Technical Environment
Special processor, for communication and data exchange between
satellite on the orbit and ground based station. Pilot project at
65nm STM Space technology.
Description
Client Reference :
Airbus Defence & Space (Astrium), Germany

11. SETUP OF HIERARCHICAL TEST CONCEPT
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References Project of Michael Kogan (michael.kogan@ic-link.eu) 11
• Hierarchical scan insertion
• Hierarchical scan chain compression macro (EDT) insertion
• Core Isolation (Core Wrapper Chains insertion, IEEE 1500)
• Hierarchical ATPG (INTEST, EXTEST)
• Pattern Retargeting
• Internal JTAG (iJTAG, IEEE 1687): test of embedded instruments, 3rd party IP
• Test point insertion
• Cell aware ATPG
• Stuck-at, at-Speed, IDDQ, pseudo random (LBIST) test pattern generation (ATPG)
• Test patten simulation, w/wo SDF
Tasks
 Synopsis Design and DFT Compiler
 Mentor Tessent and Modelsim
 Cadence NCsim
Technical Environment
Setup of Hierarchical Test Concept to be used for next generation of
complex chips. EDA tools evaluation.
Description
Client Reference :
Infineon AG, Germany

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References Project of Michael Kogan (michael.kogan@ic-link.eu) 12
RECOMMENDATIONS AND REFERENCES

13. CUSTOMER‘S FEEDBACK 1
MOHSIN SYED
PROJECT MANAGER
AIRBUS DEFENSE & SPACE
ROLAND WEIGAND
VLSI/ASIC ENGINEER
AT EUROPEAN SPACE AGENCY
 “Michael Kogan was hired to support our team
with the implementation (Backend design viz.
Synthesis, STA and Test Vectors
generation(ATPG)) of a complex ASIC in
radiation-hardened technology. In addition, he
has also supervised the P&R, floorplanning,
clock tree synthesis and timing closure tasks
performed by the ASIC Vendor.
Thanks to his contribution, the time critical
project was completed on time and design
performance parameters were met. Michael
has proven himself as an expert in ASIC
implementation, a team player committed to
achieve the project goals. We look forward to
continue work with Michael on the next
project.”
 “Michael has provided excellent design
services during one of our IC developments.
He was mainly involved into DFT insertion and
test generation, and he also provided general
expertise and help during synthesis,
verification and layout. It was a pleasure to
have him in the team .”
03.05.2016
References Project of Michael Kogan (michael.kogan@ic-link.eu) 13

14. CUSTOMER‘S FEEDBACK 2
GUY NAVARA
PHYSICAL DESIGN TEAM LEADER
ALTAIR SEMICONDUCTOR
JIM CARLQUIST
DESIGN ENGINEER
FREESCALE SEMICONDUCTOR
 “I hired Michael as a DFT
consultant/Engineer for our last project,
this is not the first time Michael worked for
Altair Semiconductor and surely not the
last.
Michael demonstrated the exceptional
engineering ability required to understand
and apply the various DFT concepts for our
complicated chip.
I have found Michael to be a responsible,
sincere, and an all-around respectable
person. Michael's self-motivation and keen
desire to learn new topics and solve
problems are to be commended.
It was my great pleasure to have Michael as
a DFT consultant. I strongly recommend
Michael into your firm.”
 I worked with Michael this year on a rebuild of
an old project that was originally designed
several years in an obsolete tool set. The
project had been moving along very slowly with
resources in various locations around the
world until Michael joined the team. His
expertise and experience pushed the project
along and Michael started with chip our floor-
plan and synthesized netlist and completed
everything including design flow updates,
timing constraints, highlighting and fixing
timing issues, and was able to complete the
project using Cadence Encounter. I would be
happy to work with him on other projects in the
future.
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References Project of Michael Kogan (michael.kogan@ic-link.eu) 14

15. REFERENCES
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References Project of Michael Kogan (michael.kogan@ic-link.eu) 15
More recommendations can be found :
 https://www.linkedin.com/in/michaelkogan
 http://www.ic-link.eu/references.html
Most recent training certificates:
 http://www.ic-link.eu/certificates.html
Online CV
 http://www.ic-link.eu/cv.html

16. CONTACT DETAILS
Email: michael.kogan@ic-link.eu
Mobile Phone: +49(0) 176 802 88 245
WEB SITE: http://www.ic-link.eu
Online contact: http://www.ic-link.eu/contacts.html
03.05.2016References Project of Michael Kogan
(michael.kogan@ic-link.eu)
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