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MIPI DevCon 2016: MIPI D-PHY - Physical Layer Test & Measurement Challenges

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The D-PHY specification, since the release of its first version more than a decade ago, continues to evolve and push the envelope of throughput to support current and future needs of mobile interfaces – camera and display in particular. In this process, PHY layer test and measurement solutions are posed with newer challenges to provide for the feature additions to the specification. This presentation by Parthasarathy Raju and Suryakant Kumar of Tektronix discusses an introduction to both transmitter and receiver characteristics of D-PHY, and highlights the importance of test modes. Also discussed are test/measurement solutions to overcome these challenges and simplify the testing of devices to accomplish conformance.

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MIPI DevCon 2016: MIPI D-PHY - Physical Layer Test & Measurement Challenges

  1. 1. MIPI D-PHY℠ - Physical Layer Test & Measurement Challenges Parthasarathy Raju, & Suryakant Kumar, Tektronix
  2. 2. Agenda • MIPI D-PHY℠ Spec Overview •  New in v2.0 • PHY layer Testing •  Transmitter & Receiver Needs •  Equipment •  Device Test Modes 2
  3. 3. MIPI: Mobile System Diagram MIPI D-PHY℠ Applications: MIPI Camera (CSI℠) & MIPI Display (DSI℠) 3 Camera & Display
  4. 4. D-PHY Lanes and Modes •  Data & Clock Lane •  Minimum configuration with 4 wires •  Data+, Data- & Clock+, Clock- •  Lane operating modes •  High Speed Mode(HS) •  Terminated •  Low swing, Differential signal •  Non-Return to Zero(NRZ) coding •  Data transmission •  Low Power Mode(LP) •  Non-Terminated •  Single-ended transmission •  Spaced-One-Hot coding •  Control 4 Data+ Data- D-PHY Clock+ Clock-
  5. 5. HS Data Transmission in Bursts •  Continuous Mode & Burst Mode •  Four LP states •  LP-00, LP01, LP-10, LP-11 •  Stop state(LP-11) – Standby state 5 Clock : Burst Mode
  6. 6. Data to Clock Timing •  Differential Data to Clock has a quadrature phase relationship •  Data-Clock Timing Specification •  Data to Clock Skew •  Setup time & Hold time •  Deterministic and Random Jitter( data rate > 1.5Gbps) 6 Parameter Min Max TSKEW[TX] (UI) -0.2 0.2 TSETUP[RX] (UI) 0.2 THOLD[RX] (UI) 0.2 TSKEW[TLIS] (UI) -0.1 0.1 Parameter Min Max TJTX(UI) 0.3 DJTX(UI) 0.2 RJTX(UI) 0.1 TSKEW[TX] staAc (UI) -0.2 0.2
  7. 7. HS-Transmitter •  Half Swing Mode •  Differential swing of Tx is half with respect to default swing mode •  Option for reduced operating power •  De-emphasis •  Two equalization ratios are defined •  Data rates >2.5Gbps 7
  8. 8. SSC & Eye Diagram •  Spread Spectrum Clocking •  Triangular Down spreading, deviation 5000ppm at 33KHz •  Transmitter & Receiver Eye Diagram •  Data Rates >1.5Gbps & <= 4.5 Gbps •  Reference channel included •  Mask prorated to BER 10e-6 8 BER TEYE VDIF 10-12 0.5UI 40mV 10-6 0.53UI 47mV
  9. 9. Interconnect Spec & System Configurations •  Three Differential Insertion loss templates •  Short, Standard & Long Reference •  Uniform reference across all MIPI PHYs 9 Mode # Data Rate Gbps TransmiPer Swing EQ Reference Channel Receiver Term (ohm) 1 Default EQ2 Short/Std 80-125 2 Long 3 Half Swing EQ1 Short 4 Std 5 Long 6 Short/Std NT 7 Long 8 None Short 9 Std 10 Long
  10. 10. Receiver De-skew Calibration •  Operating data rates >1.5Gbps •  Initial and Periodic Calibration modes •  De-skew burst •  Sync : all one’s (16UI) •  Payload: 0101 (215 UI) 10
  11. 11. LP-Transmitter, LP-Receiver •  Line Levels •  VOL(Min)= -50mV, VOH(mx) = 1.3V •  Slew rate spec for various load conditions •  LP Receiver - Interference and Noise performance •  Input pulse rejection(eSpike) •  Minimum pulse width response(TMIN-RX) •  Peak Interference(VINT, fINT) 11
  12. 12. MIPI D-PHY℠ Test & Measurement Challenges
  13. 13. Elements of Testing •  Test Methodology •  Waveform/Pattern/Region •  Measurement Procedure/Post processing Algorithm •  Test Equipment •  Oscilloscopes •  Waveform Generators •  Probes & Accessories •  Device -Test Modes, Test Points •  Test Sequences •  Bit Error Detector •  Replica Traces •  Test Modes Needs special focus! 13
  14. 14. Tx Testing Challenges(contd..) •  Dynamic switching of terminations between LP and HS mode •  Waveform post processing to discern the LP-HS transitions •  Probing •  HS & LP transmission without loading the bus •  Access to tight test locations •  Burst Mode timing measurements •  Measurements on clock and data lanes •  Voltage and Timing parameters 14
  15. 15. Tx Testing Challenges •  Data rate up to 4.5Gb/s •  800 Mbps to 4.5G •  Eye diagram and jitter measurements •  Tx Equalization by de-emphasis •  Spread-spectrum clocking •  Embed channel insertion loss •  LP Mode •  Slew rate measurements •  Bus Turn Around test •  User intervention to enable mode and measure 15
  16. 16. Tx Testing 16 •  4 Single ended Signals •  Data+, Data- & Clock+, Clock- •  Termination Board •  Switchable Termination •  Oscilloscope & Probes •  Based on Signal data rate •  v1.0 (800 Mbps), •  v1.1 (1.5 Gbps) •  v1.2 (2.5 Gbps) •  v2.0 (4.5 Gbps) •  High impedance probes •  50+ CTS Tests TerminaAon Board
  17. 17. Device Test Modes for Tx Testing •  LP Mode Measurements •  LP sequence with open termination •  BTA initiation •  HS Mode Measurements •  HS entry •  HS Sync & Payload •  Random Test sequences (PRBS) •  HS exit •  Data and clock lanes •  Continuous and Burst Modes 17
  18. 18. Tx Test: Spread Spectrum clocking •  SSC Testing •  Modulation Rate = 30KHz (min) •  Measure over =>2 SSC cycles •  Device Test Modes/options •  HS data length > 66 µsec •  HS data ‘101010…’ 18
  19. 19. Tx Test: HS Eye Diagram •  (1) Prorated Mask at BER 1E-6 •  Measurement using random test pattern of 3 million UI •  Continuous HS data(Recommended) or Data from multiple bursts •  (2)Mask at BER 1E-12 •  Sophisticated extrapolation software on oscilloscopes 19
  20. 20. Receiver Testing(contd..) •  Philosophy •  Stimulus calibration based on parameter •  Stimulus fed to the Rx •  Check for error free reception •  Equipment •  Waveform Generator •  Data and clock lanes •  Oscilloscope for Calibration •  Choice based on D-PHY spec versions •  Observables •  Bit errors detected •  ~35 CTS Tests 20
  21. 21. Receiver Testing: Stimulus(Contd..) •  Transmission Modes •  LP Mode & HS Mode •  Spaced-one-hot, •  NRZ coding •  Data to clock timing •  Setup/Hold Times •  Skew •  HS Differential & Common mode voltage •  LP voltage up to 1.3V •  Rise/Fall time control •  Continuous & Burst data •  Data & Clock Lanes •  Test sequences/patterns •  PRBS patterns of various lengths •  LP states •  Escape Mode commands •  De-skew calibration bursts •  Standby state to trigger a test sequence •  HS entry, HS Sync & HS exit 21
  22. 22. Receiver Testing: Stimulus •  HS Mode Stressors •  Random Jitter & Deterministic Jitter •  Embed Insertion loss & De-emphasis •  Spread Spectrum Clocking •  Dynamic Skew •  LP Mode Stressors •  eSpike •  Minimum Pulse TMIN-RX •  Additive Square/Sine Noise (VINT, fINT) •  Data Burst Timing •  THS_TRAIL, THS_PREPARE ,THS_ZERO, THS_REOT •  Clock Burst Timing •  TCLK_TRAIL, TCLK_PREPARE, HS_EXIT, CLK_POST •  CLK_PRE, CLK_REOT, CLK_ZERO 22
  23. 23. Receiver Jitter Tolerance •  RT/FT Control •  Insertion Loss •  Standard Channel •  DJ & VOD Control •  Static Skew •  DC common Mode •  SSC 23
  24. 24. HS Receiver Testing •  Error Detectors •  Initiating Rx ERRDET - First Big challenge! •  HS Only ERRDET Initialization Sequence – Simple and Easy! •  Rx Stress calibration •  Procedure defined for standard reference channel •  Better Accuracy with Replica Traces for calibration! 24
  25. 25. References •  [1] DRAFT Conformance Test Suite for D-PHY℠, Version 1.2r11, 11 March 2015 •  [2] Specification for D-PHY℠, Version 1.2, 01 August 2014 •  [3] Specification for D-PHY℠, Version 2.0 Revision 07, 23 November 2015 •  [4] D-PHY℠ Testing, Parthasarathy, MIPI Open Day Presentation Taipei, October 2015 25

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