Ee325 cmos design lab 3 report - loren k schwappach

EE325, CMOS Design, Lab 3: NMOS Inverter Characteristics

Colorado Technical University

P-Spice, IRF-150 Power MOSFET Inverter Analysis

Lab 3 Report
Submitted to Professor R. Hoffmeister
In Partial Fulfillment of the Requirements for
EE 325-CMOS Design

By
Loren Karl Robinson Schwappach
Student Number: 06B7050651

Colorado Springs, Colorado
Due: 5 May 2010
Completed: 19 May 2010

1


Table of Contents

Lab Objectives ........................................................................................................................................................................................ 3

Requirements and Design Approaches/Trade-Offs................................................................................................................... 3

Characteristic Curves for the IRF-150 Power MOSFET ............................................................................................................ 4

Circuit Layout......................................................................................................................................................................... 4

PSpice Simulation Results.............................................................................................................................................. 5-6

Voltage Transfer Function of the IRF-150 Power MOSFET .................................................................................................... 6

Circuit Layout......................................................................................................................................................................... 7

PSpice Simulation Results.................................................................................................................................................. 8

Truth Table ............................................................................................................................................................................. 8

Power Consumption of the IRF-150 Power MOSFET................................................................................................................ 9

PSpice Simulation Results.................................................................................................................................................. 9

Small Signal Characteristics of the IRF-150 Power MOSFET............................................................................................... 10

Circuit Layout...................................................................................................................................................................... 10

PSpice Simulation Results............................................................................................................................................... 10

Frequency Response of the IRF-150 Power MOSFET ............................................................................................................ 11

Circuit Layout...................................................................................................................................................................... 11


Propagation Delay and Rise/Fall Times of the IRF-150 Power MOSFET ........................................................................ 12

Circuit Layout...................................................................................................................................................................... 12


Digital Frequency Response of the IRF-150 Power MOSFET .............................................................................................. 14

PSpice Simulation Results......................................................................................................................................... 14-15

Maximum Frequency of the circuit using the IRF-150 Power MOSFET .......................................................................... 16


Summary of Results ........................................................................................................................................................................... 17

Conclusion and Recommendations .............................................................................................................................................. 17

2


Lab Objectives

This objective of this lab is to introduce the user into the use and features of one of the most

popular analog and digital simulation software packages, PSpice (specifically OrCAD Capture

CIS Demo Version 15.7). As an added bonus the user should complete this lab assignment with

a greater understanding of the common characteristics of a commercially available n-channel

MOSFET. This lab is designed around the IRF-150 Power MOSFET. The lab will evaluate the

inverter characteristics of the IRF-150 by generating device characteristic curves, voltage

transfer function, frequency response diagram (bode plot), and time domain analysis of specific

frequencies needed to compute the IRF-150’s characteristic rise/fall times, and propagation

delays.

Requirements and Design Approaches / Trade-offs

There are no specific design requirements for this project since it is not a design project, but a

PSpice learning lab. The primary objective of this lab is to learn the procedures and methods in

using the PSpice simulation software to identify and analyze key characteristics of the IRF-150

inverter circuit. This circuit and data collected through this lab will be compared against in later

labs.

3


Characteristic Curves for the IRF-150 Power MOSFET

In order to begin analyzing the IRF-150 inverter, you must have OrCAD 15.7 Demo installed
(or a later, working variant). Next open OrCAD Capture CIS and create a new project using
Analog / Mixed (A/D). After the project space is ready a design schematic should be built
as shown in figure 1 below. Building a schematic is as simple as laying down parts and
connecting the components with wire. The main PSpice parts/components we will use in
this lab are (IRF-150, VDC, VAC, VPULSE, 0Ground, C/ANALOG, R/ANALOG, and Net Alias).
Once you have everything pieced together, you are ready to run a PSpice simulation. First,
create a new simulation profile for testing the transistors Id-Vd relationships. Next, set the
simulation settings to use a DC Sweep, with a Primary Sweep of “Vdrain” from 0 V to 10 V
in small 1 mV increments (figure 2), and a Secondary Sweep of “Vgate” from 0 V to 10 V
(Note, 2 V to 10 V also works) in 1 V increments (figure 3). I also simulated sweeping
Primary and Drain from 0 V to 5 V for future inverter comparisons. The results of these
simulations are seen in figures 4 and 5.

0

Vdrain
5Vdc

Vgate
M1
0
IRF150
5Vdc

0

Circuit used for generating the IRF-150
transistor curves (Id-Vd curves)

Figure 1: PSpice circuit used for IRF-150 Id-Vd curves.

4


Figure 2: DC Sweep, Primary Sweep Config. Figure 3: DC Sweep, Secondary Sweep Config.

8.0A
I
Characteristic Curves for the IRF-150
D Primary Sweep: VDrain (0-5 Vdc)
r Secondary Sweep: VDrain (0-5 Vdc) V_Vgate = 5V
a
i
n

4.0A

V_Vgate = 4V

V_Vgate = 3V Note: V_Vgate < 3V curves are not visable
0A
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
ID(M1)
V_Vdrain

Figure 4: Characteristic curves for IRF-150. (0-5V Sweeps).

5


80A
I
Characteristic Curves for the IRF-150
Primary Sweep: VDrain (0-10 Vdc) V_Vgate = 10V
D
r Secondary Sweep: VDrain (0-10 Vdc)
a
i
n
V_Vgate = 9V

40A
V_Vgate = 8V

V_Vgate = 7V

V_Vgate = 6V

V_Vgate = 5V
V_Vgate = 4V Note: V_Vgate <= 3V curves are not visable
0A
0V 1V 2V 3V 4V 5V 6V 7V 8V 9V 10V
ID(M1)
V_Vdrain

Figure 5: Characteristic curves for IRF-150. (0-10V Sweeps).

Voltage Transfer Function for the IRF-150 Power MOSFET

To generate the voltage transfer function (Vout vs. Vin) of the IRF-150 Power MOSFET, the
circuit design was updated to include a 1 kΩ resister after the VDC source “Vdrain”, and a 1
pF capacitor after the 1 kΩ resister going to ground. Two net aliases “Vout” and “Vin” were
then added until the circuit finally matched the circuit shown by figure 6.

Next the circuit simulation settings were again adjusted. After the Secondary Sweep was
removed, the Primary Sweep was updated to sweep “Vgate” from 0 V to 5 V in small 1mV
increments (figure 7). The new simulation was run with the results shown by the bottom
half of figure 8. You may need to add a trace of “V(Vout)” if you didn’t attach a voltage
probe to Vout.

Next, a line with a slope of 1 was drawn originating from (0 V, 0 V) to (4 V, 4 V). The
intersection of this line with the voltage transfer function graph of V(Vout) was noted as
the IRF-150 Power MOSFET’s logic threshold or switching point. This threshold voltage is
the point where Vin = Vout, and was determined to be approximately 2.868 V.

Next a new plot was added to graph the slope (derivative) of “Vout” (Top half of figure 8).
Creating a new plot is as simple as clicking plot/new plot and giving the new plot a trace
(In this case d(V(Vout))). The points where the new slope = -1 are used to define the noise
margins of this inverter. An easy way to find these locations is by using the search
command and typing “search forward level(-1)”. Using this technique twice to find both

6


locations where the slope = -1 the following could be defined. Once found you can identify
the specific x-value with the “search forward xvalue(###)” command, where ### is the x-
value you are searching for. After adding these coordinates the following data was
obtained.

VIH = minimum HIGH input voltage = 2.8965 V
VIL = maximum LOW input voltage = 2.8311 V
VOH = minimum HIGH output voltage = 4.9886 V
VOL = maximum LOW output voltage = 32.908 mV

Using these values the noise margins of the IRF-150 Power MOSFET were calculated as:

Noise Margin Low = NM L = VIL – VOL = 2.798 V
Noise Margin High = NMH = VOH – VIH = 2.092 V

For an Ideal Inverter:
NML = VDD/2 – 0 = 2.5 V
NMH = VDD – VDD/2 = 2.5 V

So IRF-150 NML is approx. +12% of Ideal, and IRF-150 NMH is approx. -16% of Ideal.

Vdrain
R1

1k
5Vdc Vout
0
V

C1
M1 1pF
Vin

Vgate IRF150 0
5Vdc

0

0 Circuit used for generating the IRF-150
voltage transfer function (Vout vs. Vin)

Figure 6: PSpice circuit for generating the IRF-150 Figure 7: PSpice simulation setup parameters for
voltage transfer function (Vout vs. Vin). voltage transfer function.

7


0
S
l Graph of V(Vout)'s Slope
(2.8311,-1.0000) (2.8965,-1.0000)
o Interesting points are where Slope = -1
p -50 These points determine Vin(low) and Vout(low) Slope of V(Vout) = -1 Slope of V(Vout) = -1
e Used for finding Low and High Noise Margins
-100
Point of Max Slope
(2.8860,-168.922)
SEL>>
-175
D(V(Vout))
5.0V
V
Voltage Transfer Function (Vout vs. Vin (V_Vgate))
o
NML = Vin(low) - Vout(low) = 2.798V (2.8311,4.9886)
u
t NMH = Vout(high) - Vin(high) = 2.092V Vin(low),Vout(high)
Ideal NML = 2.5V
Ideal NMH = 2.5V (2.8682,2.8650)
2.5V Logic Threshold or Switching Point
So.. NML is approx +12% of Ideal
And.. NMH is approx -16% of Ideal
This line is a drawn strait line. Vin(high),Vout(low)
It was used to find Logic Theshold (2.8965,32.908m)

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(VOUT)
V_Vgate

Figure 8: PSpice simulation results displaying voltage transfer characteristics of IRF-150 Power MOSFET.
The top plot is a graph of the slope of V(Vout) the points where slope = -1 identify the points needed to
calculate the noise thresholds of the device.

Vin Vout
0 1
1 0
Table 1: Truth table for IRF-150 Power MOSFET.

After analyzing figure 8 the truth table above (table 1) can be developed. It is obvious
from this truth table that this circuit is acting as an inverter. A Vin < 2.8311 V (Low) results
in a Vout of 5 V (High), while a Vin > 2.8965 V (High) results in a Vout of 0 V (Low).

8


Power Consumption of the IRF-150 Power MOSFET

Modifications to the circuit used in generating the voltage transfer function (figure 6) are
not required (other than switching the V-probe at “Vout” for a W-probe at “Vdrain”) for
finding the power consumed, nor are modifications to the simulation settings. By running a
simulation using a W-probe at “Vdrain” the following results were obtained as shown by
figure 9.

26mW
P
o Power Consumed as a function of Vin
Max Power = 25mW
w
e (2.8982,24.844m) (5.0000,24.996m)
r Power at Vin = 5V -> 25mW
20mW
C
o
n Previously Determined
s Logic Threshold, Switching Point
u (2.8682,10.685m)
m
e
d
10mW

Power at Vin = 0V -> 56uW
(2.8308,35.616u)
(0.000,56.129u)
Min Power = 56uW
0W

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
-W(Vdrain)
V_Vgate

Figure 9: PSpice simulation results showing power consumed by IRF-150 Power MOSFET.

As observed from figure 9, minimum power (56 µW) is consumed when the transistor is
inverting an input (Vin) logic Low (0) into an output (Vout) logic High (1), however
maximum power (25 mW) is consumed when the transistor is inverting an input (Vin) logic
High (1) into an output (Vout) logic Low (0). The power consumed at Vin = 0 V is 56µW,
while the power consumed at Vin = 5 V is 25 mW.

A complex logic circuit composed of 2000 such inverters, where half have a logic 0, and the
other half have a logic 1 could consume approx 25W of power (1000 * 56 µW + 1000 * 25
mW = 25.056 W). With today’s IC’s packing millions of transistors this much power
therefore heat is way too expensive.

9


Small Signal Characteristics of the IRF-150 Power MOSFET

In order to find the small signal characteristics of the IRF-150 Power MOSFET, the VDC
power source “Vgate” voltage was changed (see figure 10) to the threshold voltage
determined by figure 8. Next circuit simulation settings were adjusted for Bias Point
analysis, and the check box for calculating small-signal DC gain was checked. “Vgate” was
used as the simulation input source and “V(Vout)” was provided as an Output variable
name as illustrated in figure 11.

Vdrain
R1

1k
5Vdc Vout
0

C1
M1 1pF
Vin

Vgate IRF150 0
2.868Vdc

0
Circuit used for finding the IRF-150
0 small signal characteristics. Vgate is
now at threshold voltage.

Figure 10: PSpice circuit used to find the Figure 11: PSpice simulation settings for finding
small signal characteristics of the IRF-150. small signal characteristics.

Small data capture from the bottom of PSpice simulation output file…
---------------------------------------------------------------------------------------------------------------------
****SMALL-SIGNAL CHARACTERISTICS
V(VOUT)/V_Vgate = -1.137E+02
INPUT RESISTANCE AT V_Vgate = 1.000E+20
OUTPUT RESISTANCE AT V(VOUT) = 9.978E+02
---------------------------------------------------------------------------------------------------------------------
So the gain is approximately 113.7, input resistance is approximately 100 EΩ (exa-ohms)
(or higher, due to PSpice limits), and output resistance is approximately 997.8 Ω. At this
point it seems that this circuit has a good gain, extremely high input impedance and low
output impedance.

10


Frequency Response of the IRF-150 Power MOSFET

To find the frequency response of the circuit using the IRF-150 a VAC source (with 1 VAC,
and the threshold voltage VDC) was swapped for the VDC source “Vgate” as shown in
figure 12. Simulation settings were then adjusted to provide a good bode plot diagram
showing frequencies from 10Hz to 1GHz (plotted logarithmically) at 10 points per decade
as shown by figure 13. The results shown by figure 14 indicated the circuit was behaving
like a low pass filter with a corner (f * 3 dB) frequency of 56 kHz. You may need to add a
trace of “DB(V(Vout))” This indicates that frequencies less than the corner frequency will
respond better (larger gains realized) than frequencies greater than the corner frequency
(less gain realized, until eventually the IRF-150 is unable to keep up with the large
frequencies and is non-functional.

Vdrain
R1

1k
5Vdc Vout
0

C1
M1 1pF
Vin

Vgate IRF150 0
1Vac
2.868Vdc
0
Circuit used for finding the IRF-150
0 frequency responce. Vgate is
now a VAC source at threshold DC voltage.

Figure 12: PSpice circuit used for finding IRF-150 Figure 13: PSpice simulation settings for creating
frequency response. a bode plot of the circuit’s frequency response.
45
V
g
a Bode plot for IRC-150's
i frequency response (56.410K,38.112)
n
Corner Frequency (Max -3dB)
( This is the frequency at which
d the power out is reduced to 1/2 of max
B and the voltage gain is reduced .707 of max
) We will round this frequency to 56kHz
0

.1*f(3dB) = 5.6kHz, Max VGain
f(3dB) = 56kHz, .707 of Max VGain
10*f(3dB) = 560kHz, Poor Gain

-50

Note: The IRC-150 acts like a LP Filter (Approx 6dB / decade)
-65
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz
DB(V(Vout))
Frequency

Figure 14: PSpice simulation results (bode plot) of circuits frequency response. Corner freq = 56.410 kHz.
You should observe that frequencies below 10 kHz receive great gain and allow the IRF-150 switching speeds
to approximate that of an ideal inverter.

11


Propagation Delays of the IRF-150 Power MOSFET

The circuit was again modified by replacing the VAC source “Vgate” with a Vpulse source as
shown by figure 15. This figure was used in conjunction with the variable values used in
table 2 for analyzing the circuits propagation delay (current) and digital frequency
response (upcoming) sections of this report. For each simulation a Time Domain Analysis
was performed to allow the user to see 3 to 5 periods (run to time = 3 to 5 * PER), and step
size around 1/1000 of each period as shown by figure 16. Simulation results are shown on
figure 17.

Table 2: Variables used by PSpice circuit (figure 15). Vdrain
R1

Vpulse : variables used for IRF-150 PSpice schematic 1k
5Vdc Vout
Time-Rise 0
&
Period Pulse Width V
Frequency (Hz) Time-Fall
(PER) (s) (PW) (s) C1
(TR & TF) M1 1pF
Vin
(s)
V1 = 0 Vgate IRF150 0
f3db = 56 kHz 17.857 µs 8.9286 µs 1 ns V2 = 5
TD = 0
.1 * f3db = 5.6 kHz 178.57 µs 89.286 µs 10 ns TR = 1ns
TF = 1ns 0
10 * f3db = 560 kHz 1.7857 µs .89286 µs .1 ns PW = 8.9286us Circuit used for finding the IRF-150
PER = 17.857us 0 propagation delays and digital frequency
responce. Vgate is now a Vpulse source
and TR/TF, PW, and PER will vary by freq.

Figure 16: PSpice simulation settings for finding the
IRF-150 propagation delays and digital responses.
Run to time should be 3-5 * PER, and step size should
= TR / TF.

Figure 15: PSpice circuit for finding the IRF-150
propagation delays and IRF-150 digital response at f(3
dB), .1 * f(3 dB), 100 * f(3 dB). V1 = 0, V2 = 5, TD = 0,
and TR/TF/PW/PER come from table 1.

12


6.0V
V (35.765u,5.0000)
o Rise / Fall Times and Propagation Delays
(31.931u,4.5000) (35.717u,5.0000)
l Frequency = f(3db) = 56kHz
t t(LH) rise = 4.453us
a t(HL) fall = 21ns
g Parasitic
prop. delay (LH) = 1.649us
e (35.768u,4.5000) Capacitance
4.0V prop. delay (HL) = 13ns t(LH)
.1Vdd to .9Vdd
Max Switching Freq = 223.5 kHz
tP (Prop Delay Time) = 831ns t(HL)
.9Vdd to
(28.899u,2.5000) (35.778u,2.5000) .1 Vdd

2.0V

Parasitic
Capacitance (27.478u,500.000m)
(35.789u,500.000m)
tp(LH) = time to rise from 0 to 2.5V
0V (27.125u,0.000) tp(HL) = time to fall from 5 to 2.5V (35.804u,7.9055m)
Approx 0V

26us 28us 30us 32us 34us 36us 37us
V(Vout)
Time

Figure 17: PSpice simulation results showing rise time, fall time and propagation delays of circuit at input
freq. = 56 kHz.

From the results above we can calculate the following.. Note small error in tPHL and tP may
be the result of the two points that reach 5 V. I used the right most point. The large off-
shots above 5 V and below 0 V are due to the parasitic capacitance and resistance of the
IRF-150 model.

tHL = the time it takes output voltage to drop from 4.5 V to .5 V
tLH = the time it takes output voltage to rise from .5 V to 4.5 V
tPLH = the time it takes output voltage to rise from 0 to 2.5 V
tPHL = the time it takes output voltage to fall from 5 V to 2.5 V

tHL = 35.789 µs – 35.768 µs = 21 µs
tLH = 31.931 µs – 27.478 µs = 4.453 µs
tPLH = 28.899 µs – 27.125 µs = 1.774 µs
tPHL = 35.778 µs – 35.765 µs = 13 µs

Max Switching Frequency = = 223.5 kHz
tP = Propagation delay time = .5 * ( tPLH + tPHL) = 831 ns

13


Digital Frequency Response of the IRF-150 Power MOSFET

Now the IRF-150 Power MOSFET inverters digital response is analyzed using the circuit
from the previous section (figure 15) and substituting for the frequencies provided by
table 2. The digital response is checked first at the corner frequency of 56 kHz (as done
previously), then at 5.6 kHz, and finally at 560 kHz. The results follow (Note, you will need
to read the captions next to each figure for an understanding of the results)…

6.0V
V
o (17.858u,4.9493) (38.451u,5.0000) Frequency = f(3dB) = 56kHz
l
t
a
g
e
4.0V

2.0V

(9.2807u,16.438m) (31.057u,0.000)

0V

0s 10us 20us 30us 40us 50us 60us 70us 80us
V(VOUT) V(Vin)
Time

Figure 18: PSpice simulation results showing digital response of output at frequency of 56 kHz. Note the red
is the input square pulse (Vin), and the green is the output inverted response (Vout). This is acting as an OK
inverter since the output reaches over 90% of the operating range within a pulse width, however this
response should improve with a lower input frequency.

14


6.0V
V
o Frequency = .1 * f(3dB) = 5.6kHz
l
t
a
g
e (535.044u,4.9888) (605.973u,5.0000)
4.0V

2.0V

0V

450us 500us 550us 600us 650us 700us 750us 800us 850us 900us 950us 990us
V(VOUT) V(Vin)
Time

Figure 19: PSpice simulation results showing digital response of output at frequency of 5.6 kHz (.1 * corner).
Notice the digital response is much cleaner now and is nearly that of an ideal inverter.

5.0V
V
o Frequency = 10 * f(3dB) = 560kHz
(4.1594u,5.0000)
l
t
a
g
e

2.5V

(3.5722u,818.259m)

0V

2.6us 3.0us 3.5us 4.0us 4.5us 5.0us 5.5us 6.0us 6.5us 7.0us 7.5us 8.0us
V(VOUT) V(Vin)
Time

Figure 20: PSpice simulation results showing digital response of output at frequency of 560 kHz (10 * corner).
Notice the digital response is horrible now. The IRF-150 Power MOSFET simply cannot switch fast enough
to follow the input signal. This is now a non-functional inverter.

As observed from figures 18 thru 20 above, the lower the frequency is with respect to the
corner frequency the better the IRF-150 Power MOSFET performs as an inverter. As the
frequencies increase much higher than the corner frequency the IRF-150 cannot switch fast
enough to follow the input signal (the rising edge time constant is too long per the
switching speed.). This is due to the internal capacitance of the MOSFET.

15


Maximum Frequency of the IRF-150 Power MOSFET circuit

The maximum frequency is the frequency at which the output just reaches 90% or 10% of
the operating range within a pulse width. Finding the maximum frequency is done through
a little trial and error. Using the corner frequency as a starting position the frequency was
incrementally increased until the output reached 90% of VDD = 4.5 V. This was found to be
approximately 100 kHz, as shown in figure 21 below.

6.0V
V
o Approximation of Max Frequency Response
l Output Reaches Approx 90% of Operating Range
t By slowly increasing frequencies this freq. was found
Approx 4.5V -> 90% of 5V
a Frequency = 100kHz
g (10.000u,4.4542)
e
4.0V

2.0V

0V

5us 6us 7us 8us 9us 10us 11us 12us 13us 14us 15us
V(VOUT)
Time

Figure 21: PSpice simulation results of testing freq. = 100 kHz as maximum frequency. Notice output reaches
approx 4.5 V.

16


LAB 3: Summary of Results
IRF-150
Evaluation Ideal
Parameter Inverter
Procedure Inverter
Circuit
Transfer Char. VThreshold 2.5 V 2.8682 V
Noise NMH 2.5 V 2.092 V
Margins NML 2.5 V 2.798 V
P@0V 0W 56 µW
Power P@5V 0W 25 mW
PMax 0W 25 mW
Rise Time tLH 0s 4.453 µs
Fall Time tHL 0s 21 ns
tPHL 0s 13 ns
Propagation Delays tPLH 0s 1.774 µs
tP 0s 831 ns
Small Signal Gain Av ∞ -113.7
Rin inf. inf.
Impedances
Rout 0 997.8
3dB Corner
f3dB N/A 56.23 kHz
Frequency
Maximum
fMax N/A 100 kHz
Frequency
Table 3: Summary of Results for LAB 3.

Conclusion and Recommendations

As mentioned in previous sections for an ideal inverter (VIL=VIH=Vdd/2=2.5 V, VOH = Vdd=5 V,
VOL=0 V, Noise margins = 2.5 V) and as displayed by table 3 above, the IRF-150 NML is 12%
of the Ideal NM L, while the IRF-150 NMH is -16% of the Ideal NM H. Also noted was the IRF-
150 works best as an inverter at frequencies below 10 kHz because its frequency response
closely resembles a low pass filter with a corner frequency of approximately 56 kHz. Because of
these reasons, I would say that the IRF-150 could be used as an inverter for simple low
frequency circuitry. Also, as mentioned in the power consumption section, each IRF-150 takes
either 56 µW or 25 mW depending upon the state of the inverter. This can create huge problems
in IC’s that require several of these devices to function, but since this is a Power device its
application in the digital world is not as relevant. With its long propagation delay’s and rise/fall
times cause by internal resistance and capacitance this inverter is not well suited for high
frequency applications.

17

Ee325 cmos design lab 3 report - loren k schwappach

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