JP Keynote Nikkei Embedded Processor Symposium 2002
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JP Keynote Nikkei Embedded Processor Symposium 2002
- 1. At the core of the user experience.™ John Bourgoin Chairman & CEO October 30, 2002 Nikkei Embedded ProcessorNikkei Embedded Processor Symposium 2002Symposium 2002
- 2. At the core of the user experience.TM The Digital World
- 3. At the core of the user experience.TM Changing Forces in Design Decisions 90nm technology changes the rules…. Product lifecycles shrinking faster….. Rapid processor performance increases coupled with exploding NRE’s dictate that programmable devices will take a larger share of the SOC function These require a change in design approach…
- 4. At the core of the user experience.TM DSPs, Specialty Processors DSPs, Specialty Processors Options for the SOC Developer MicroprocessorsMicroprocessors Dedicated Hardware Dedicated Hardware Flexibility, Adaptability, Upgradability Source: John Hennessy Perfo
- 5. At the core of the user experience.TM Key Questions for Solutions Options 1. Can it perform the application? Performance, power, feature set, etc. 2. Can it meet the cost needs for the market? Combination of NRE, unit, and opportunity costs 3. Can I get it to market early? Or at least early enough
- 6. At the core of the user experience.TM Increasingly, Programmable Solutions are the Answers Why? Standard, programmable cores increasingly address all three issues as performance grows rapidly.
- 7. At the core of the user experience.™ Question 1: Can it perform the function?
- 8. At the core of the user experience.TM Historical Perspective Performance Time Programmable Microprocessor Performance Needed by Market for a Given Function Hard-wired Logic or Specialized Processor Performance Gap Time-to-Market Sacrifice Headroom for Other Functions
- 9. At the core of the user experience.TM Cheap Transistors Change the Game Programmable Microprocessor Hard-wired Logic or Specialized Processor Performance Gap Time-to-Market Sacrifice Invest transistors to boost processor performance, recover time to market. Performance Time
- 10. At the core of the user experience.TM New Systems Need Performance More features and functions each generation Device convergence adding complexity Greater streaming media content High computational loads High throughput demands High task capacity Real-time deadlines Security issues Quality of service Meeting these challenges with a programmable solution requires very high performance Traffic shaping Load balancing “Deep” packet processing Billing and statistics Stateful firewalls Interactive video Wireless games Wireless local loop 4G 3G W/CDMA CDMA-2000 IP over Sonet IPv6 Peer-to-peer VoP Internet edge routing MPLS QoS Multi-service processors AES IPSec OC-768 OC-192 802.11a Artificial intelligence Voice synthesis Voice recognition Virtual reality Digital TV HDTV AAC 3D Audio RAID Videoconferencing Multimedia MPEG4 MPEG2 Video processing Image processing Streaming video JPEG2000 Data compression Software radio Vocoding xDSL Soft Peripherals Steerable antenna arrays Powertrain control Navigation systems Telematics Digital radio High-realism 3D animation Games AC-3 MP3 WMA RSA Moore’s Law to the rescue
- 11. At the core of the user experience.TM Performance per $ Accelerates 0.5 0.81 1.31 2.1 3.4 5.4 8.7 14 22.5 36 58 94 150 242 389 625 1005 1615 0 200 400 600 800 1000 1200 1400 1600 1800 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 0x 500x 1000x 1500x 2000x 2500x 3000x 3500x Integer performance per dollar increasing at 61% per year MIPSper$ ImprovementSince1990 Source: ITRS & MIPS TechnologiesSource: ITRS & MIPS Technologies
- 12. At the core of the user experience.TM Effective Performance Will Increase Even Faster! Architecture enhancements will boost streaming-media performance even higher Advanced microarchitecture techniques will: Increase utilization of existing transistors, which boosts processor throughput and response times Increase processor tolerance to slow memories Chip multiprocessing will exploit additional levels of parallelism Floating-point performance rising even faster than integer
- 13. At the core of the user experience.TM Dedicated Hardware Dedicated Hardware DSPs, Specialty Processors DSPs, Specialty Processors Options for the System Developer MicroprocessorsMicroprocessorsMicroprocessorsMicroprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Microprocessors High-Performance Augmented Microprocessors High-Performance Augmented Microprocessors High-Performance Augmented Microprocessors High-Performance Augmented Microprocessors Flexibility, Adaptability, Upgradability Perfo High-Performance Augmented Microprocessors High-Performance Augmented Microprocessors
- 14. At the core of the user experience.™ Question 2: Can it meet the cost needs of the market?
- 15. At the core of the user experience.TM Mask Costs Go Ballistic $0K $200K $400K $600K $800K $1,000K $1,200K 0.35µ 0.25µ 0.18µ 0.13µ 0.10µ Process Technology Node MaskCostsperSet
- 16. At the core of the user experience.TM 2003 NRE Costs Skyrocket Design Costs Mask Costs Mfg. Costs $0M $1M $2M $3M $4M $5M $6M $7M $8M $9M $10M 1995 (0.35um) 1997 (0.25um) 1999 (0.18um) 2001 (0.13um) 2003 (0.10um) Design 100% Mfg. (250KU) Assumptions: 6M → 70M transistors, 3 mask spins, 250K Units, transistor costs and productivity projected from the ITRS 62% Masks Design 100% Masks Mfg. (250KU) 1995 13%
- 17. At the core of the user experience.TM Die Cost Impact of Low Volumes: Total Cost of Production $53.75 $19.67 $7.99 $4.57 $3.38 $3.04 $0.00 $10.00 $20.00 $30.00 $40.00 $50.00 $60.00 100K 300K 1M 3M 10M 30M Unit Volumes TotalCost/Die Fully Amortized Die Cost Assumptions: $2M mask charge, 25 wafer min lot size, $3000/300mm wafer, $3M dev cost
- 18. At the core of the user experience.TM Programmability Leverages Design Costs Across Multiple Products Right first time Simpler designs More design reuse Broader applicability Memory AFE 10/ 100 Phy Memory Control Std Per Voice band AFE 10/100 MAC Standard Peripherals Hardware AAL DSL Phy Security Vocoders & Fax (DSP) µP Core
- 19. At the core of the user experience.TM Programmability Lowers NRE Lower total mask costs Software flexibility increases 1st silicon success Reuse of known-good processor cores Product changes without hardware redesign Fewer silicon spins (fewer mask sets) Lower design costs Less complex SOC designs (vs. alternatives) Greater reuse of hardware blocks (processors) Reuse complete SOC designs in other products and in upgraded products
- 20. At the core of the user experience.™ Question 3: Can I get it to market early?
- 21. At the core of the user experience.TM One Million Units Time-to-Market Is Vital 0 2 4 6 8 10 12 14 16 18 20 Years After Introduction SalesVolume B&W TVCable TVColor TVVCRPCCellularPCS DVBDVD The impact of being late to market is becoming more significant Source: Semico Research
- 22. At the core of the user experience.TM The Value of Time-to-Market Time-to-market is an increasingly large factor in a product’s total integrated profit Assumes: 18 month market ramp, 40 month product life, $10M NRE, 50% margins -20% 0% 20% 40% 60% 80% 100% 120% 0 3 6 9 12 15 Months Late Profits
- 23. At the core of the user experience.TM Time-in-Market Boosts Integrated Profit Time Dwell Time in Market Longer Time at Higher Profitability Hardwired Solution Programmable Solution Flexibility Extends Time-in-Market Flexibility Reduces Design Time and NRE RevenueCosts Sooner to Revenue Profit NRE Unit Costs
- 24. At the core of the user experience.TM Programmability Speeds Time-to-Market and Extends Time-in-Market Reduced SOC development time Late binding of product features: start design early, finalize after tape-out Adaptability to late changing standards Greater design reuse, higher productivity Extended product lifetime Tweak to match changing market conditions Protection from obsolescence Reuse SOC in derivative products Reuse SOC in adjacent products
- 25. At the core of the user experience.™ Key to Success
- 26. At the core of the user experience.™ Apply the falling cost of transistors to lower the rising costs of development
- 27. At the core of the user experience.TM Disappearing Cost of Transistors 0 50 100 150 200 250 300 350 400 450 500 1997 1999 2001* 2003* 2005* µCents/transistor * Source: ITRS 2001, packaged parts + 60% GPM -30% / year
- 28. At the core of the user experience.TM Strategy for the Future Apply falling transistor costs to Higher-performance processor cores Enabling more programmable solutions Giving lower NRE, faster time-to-market Thus lower costs, higher revenues And, increased profits How? 8 32 64 128-bit architectures Vector processing, data-parallel SIMD ALUs Fine-grain multithreading High-frequency instruction-parallel pipelines Chip multiprocessing (CMP)
- 29. At the core of the user experience.™ Processor Performance Increasingly Will Be Applied to Improve NRE & Time in Market
- 30. At the core of the user experience.™ Thank You