mosfet scaling_

ENG: KHAIRI AHMED ELRMALI UNIVERSITY OF MALAYA
1
FACULTY OF ENGINEERING
(INDUSTRIAL ELECTRONIC AND CONTROL)
MICROELECTRONIC TECHNOLOGY
(KXGK6302)
MOSET Lab – Worked out problems
KHAIRI AHMED ELRMALI
KGK1500011
SUBMITTED TO: DR. NORHAYATI BINTI SOIN
Semester I
Academic Session 2017

2
MOSFET Lab Report
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect
Transistors (MOSFETs), their structure and principle of operation. Then it details the
fabrication and characterization of the MOSFETs fabricated at the microelectronic lab
at University of Malaya
Samoset tool simulates the current-voltage characteristics for bulk and SOI Field Effect
Transistors (FETs) for a variety of different device sizes, geometries, temperature and
doping profiles.
( http://nanohub.org/tools/mosfet )
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several
powerful analytic features of this tool are demonstrated, including the following:
➢ calculation of Id-Vg curves
➢ potential contour plots along the device at equilibrium and at the final applied bias
➢ electron density contour plots along the device at equilibrium and at the final
applied bias
➢ spatial doping profile along the device
➢ 1D spatial potential profile along the device
Basic device configuration
The basic structure of a MOSFET is illustrated in Fig.1. The figure shows an n-type
MOSFET structure which is relative to the type of the inversion layer (channel) created.
Basic device parameters:
Gate: Polysilicon or Metal (eV)
Oxide: SiO2 used as the dielectric (nm)
Channel: n-type doped semiconductor for PMOS and p-type doped for NMOS
Source/Drain: Heavily doped regions in contact with channel
Substrate: Base semiconductor material

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channel length L - channel width W oxide thickness tox junction depth rj - substrate
doping NA
Fig 1shows a MOSFET cross section
There are basically four types of MOSFETs:
n-cnannel, enhancement mode device n-cnannel, depletion mode device
p-cnannel, enhancement mode device p-cnannel, depletion mode device
Positive gate voltage does two things:
(1) Reduces the potential energy barrier seen by the electrons from the source and the
drain regions.
(2) Inverts the surface, and increases the conductivity of the channel.
Substrate
Source DrainChannel
Oxide
Gate

4
Input values for the various parameters by change the default data
Structural properties: General properties of the materials used such as physical
dimension and doping
Mode:
Toggle simulation parameter (silicon parameter – oxide parameter) also define the
effects the surroundings (temperature)
Voltage sweep: define the effects applied voltage (Vg-Vd) vary the gate and drain
voltage with respect to ground in this simulation model
Simulate three generations of devices with parameters specified in the table below
with and without impact ionization included in the model

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Channel length Substrate Oxide thikness Vd Vg
100 nm 1e+17 3nm 0 to 1.8 1-1.4-1.8
Fig IV-characteristics MOSFET (ID vs VD)
movement of carriers under the influence of an electric field
Initial bias Final bias
Various modes of operation of a MOSFET Electric field
Saturation
region
Linear region

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IV-characteristics MOSFET (Id vs Vg)
Input parameter
45 nm 5e+17 2nm 0-1.2 0.8-1-1.2
Fig IV-characteristics MOSFET (ID vs VD)
DIBL= 41.88mV/V
Vt =~ 0.48 V
SS ~78.6mV/dec
Ion/Ioff =85.2153x10-3
SS
DIBL
Ioff
Ion

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Fig IV-characteristics MOSFET (Id vs Vg)
Mobility is important because the current in MOSFET depends upon mobility of
charge carriers(holes and electrons).
DIBL= 154.73 mV/V
Vt =~ 0.23 V
SS ~ 203.47mV/dec
Ion/Ioff =81.73

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Electric field
Initial bias final bias
Fig :Various modes of operation of a MOSFET Electric field
Input parameter
25 nm 1e+17 1nm 0-1 0.6-0.8-1
channel length is reduced, the horizontal electric field between the source and
drain increases to a point where the carrier mobility becomes zero,

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Electric field initial doping
Table 1: illustrate performance for different MOSFET
Lc Vth DIBL SS Ion Ioff Ion/Ioff
100nm
vd=1.8
0.48 41.88mv/v 78.6em
v/dec
0.415e-3 4.87e-9 85.215e-3
45 nm
Vd=1
0.23 154.73mn/v 203.47
m/dec
0.81e-3 9.898e-6 81.73
25 nm carrier mobility becomes zero
(a) Are these well designed devices? Why or why not?
Device with 100nm : device is reduced the drain induced barrier lowering
{DIBL=41.88mv/v < 100 mv/v }(means small variation of threshold voltage at
low and high drain voltage) and better {ION/IOFF=85.215e-3} ratio is achieved. This
device is useful to overcome the short channel effects according to above table
Device with 45nm : from the above table {DIBL 154.73mv/v}This effect occurs
in device where only the channel length and oxide thickness is reduced without
properly scaling the other dimensions,as seen in the Id vs Vg graph above,the
threshold voltage begins to decrease and {Ioff=9.89e-6} leakage current at off
state device increased Velocity saturation these can lead to substantial off-
currents and power dissipation

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Device with 25nm: device totally useless Due to the high electric fields that result
in short-channel As a side effect, surface scattering becomes heavier, reducing the
effective mobility Surface scattering
# I noticed limited all 2D plots at final bias just at initial bias
(b) If not, what has to be changed in terms of device parameters?
In theory, there are two methods of scaling:
1) Full-Scaling (also called Constant-Field scaling): In this method the device
dimensions (both horizontal and vertical) are scaled down by 1/S, where S is the
scaling factor this usually the case.
Pro: avoids nasty high field issues, plus competition between gate and drain.
Con: can’t keep reducing voltages forever
2) Constant-Voltage scaling (CVS): In this method the device dimensions (both
horizontal and vertical are scaled by S, however, the operating voltages remain
constant.
Pro: maintains voltages at reasonable levels.
Con: run into all the high field effects
Comparison of the effect of scaling on MOSFET device parameters. Compared are constant field
scaling, constant voltage scaling and constant voltage scaling in the presence of velocity saturation.

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(c) Is punch-through effect observed in any of these devices? Why or why not?
Punch- effect observed in n-type MOSFET’s with a channel length of 45nm and
25nm. In sufficiently small devices, the depletion regions from the source and drain
can actually merge. This is particularly awkward since the drain depletion region is
strongly altered by Vd, Vg only influences small volume near surface. Current can
flow through depletion zone “space-charge-limited” ~ V2
d
• How to mitigate? Higher doping concentration in bulk wafer leads to shorter
depletion widths, though there is an upper limit to reasonable doping.
(d) Are these devices operating in the velocity saturation regime or not?
As the channel length is reduced, the horizontal electric field between the source and
drain increases to a point where the carrier mobility becomes zero, In the limit the
short-channel device will have a saturation current of:
IDSat = Cox*W*K (VGS – Vth)n
VDS < VGS-Vth (Velocity Saturation)
Device with 100nm NA = 1018
cm-3
, tox = 3 nm as characteristics MOSFET (ID
vs VD) that device operating in strong inversion (vGS > VT) and SS= 78.6emv/dec
Device below 45 nm ,tox = 2 nm
reduced with scaling such as the MOSFET oxide thickness and the power supply
voltage. The reductions are chosen such that the transistor current density increases
Ion/Ioff= 81.73

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Conclusion
In case of long channel MOSFETs, gate has control over the channel and
supports most of the charge. As we go to short channel lengths as seen in the graph
above, the threshold voltage begins to decrease as the charge in the depletion
region is now supported by the drain and the source also. Thus the gate needs to
support less charge in this region and as a result,. This phenomenon is known as
charge sharing effect.
List of short channel effects
❖ Threshold voltage variation with channel length
✓ As channel length L decreases threshold voltage decreases
❖ Drain induced barrier lowering (DIBL)
✓ Drain voltage affect Vth
❖ Mobility degradation with vertical field
✓ Large Vgs leads to more carrier scattering and reduced mobility
❖ Velocity saturation
✓ Mobility of carrier begins to drop as electric field increase above 1V/nm

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What problems are we really trying to investigator?
There are several specific device physics problems that are addressed by these
proposals:
• Short-channel effects (lack of saturation of ID )
• Short-channel threshold modification (drain-induced barrier lowering)
MOSFET channel length every year according to the following table.
developed the capability to fabricate Bulk MOSFET
Time Year 1 Year 2 Year 3 Year 4 Year 5
Channel Length 100 nm 75 nm 50 nm 30 nm 15 nm
Process Technology
Reducing channel lengths (Lc) in MOSFET cause what is known short
channel effect (SCE). We will see some of the consequences of SCE in a NMOS
device. Consider a single gate (n+ poly) bulk type MOSFET with following
parameters.
• Source/Drain length = 50 nm
• Oxide thickness = 2 nm
• Junction depth = 20 nm
• Source/Drain doping = 2e20 /cm3
• Channel doping = 1e18 /cm3
The operating voltage for the device is .8V (Vd=0.8V)
We described an investigation of the physical properties of their influence on the
channel length modulation of MOSFET
As channel length decreases, the barrier φB to be surmounted by an electron from
the source on its way to the drain reduces
DIBL can be calculated as follows:
the Id–Vgs curve subthreshold swing (SS). The subthreshold swing is defined as

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For Lc=100nm.
Id-Vg plot for Lc=100nm.
saturation current is the drain current at a given
gate voltage (V(gate)Vdd )= Ion =9.97e-4
The leakage current is obtained at a given drain voltage at V(g)=0.0 Ioff =6.539e-8
DIBL= 0.05/(0.8-0.05)= 66.66 mV/V
Threshold Voltage, Vt =~ 0.2 V
Subthreshold slope, SS= (.1-.0)/log(6.578e-8/1.525e-8) ~ 157.52 mV/dec
Ion/Ioff = Ids(at Vg=1.5Vd=.08)/ Ids(at Vg=0,Vd=.8)=9.997e-4/6.578-8=15.19x103
DIBL= 66.66 mV/V
Vt =~ 0.2 V
SS ~ 157.53mV/dec
Ion/Ioff =15.19x103

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Id-Vg plot for Lc=75nm
DIBL= 0.05/(0.8-0.05)= 66.66 mV/V
Subthreshold slope, SS= (.1- 0.05)/log(7.5536e-6/2.0786e-6) ~ 89.233 mV/dec
Saturation and Leakage Currents: Ion = 3.351e-05 and Ioff =4.942e-07
Ion/Ioff = Ids(at Vg=1.5Vd=.08)/ Ids(at Vg=0,Vd=.8)=3.243e-5/4.9425e-8=0.656x103
DIBL= 66.66 mV/V
Vt =~ 0.1 V
SS ~ 89.233mV/dec
Ion/Ioff =0.656x103

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Id-Vg plot for Lc=50nm.
semilog Ids versus Vgs graph.
DIBL= 0.1/(0.8-0.05)= 133.33 mV/V
Subthreshold slope, SS= (.1- 0)/log(5.257e-5/1.159e-5) ~ 0.152 mV/dec
Ion/Ioff = Ids(at Vg=1.5Vd=.08)/ Ids(at Vg=0,Vd=.8)=1.126e-3/1.159e-5=1.088e3
DIBL= 133.33 mV/V
Vt =~ 0.1 V
SS ~0 .156mV/dec
Ion/Ioff =1.088e3

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For Lc=30nm.
In short channel devices, the horizontal field in the channel is high enough to reach
the velocity saturation regime, which degrades the drain current as well as the
transconductance"
After pinch off, if Vds(drain to source voltage) increased further, the channel
length(effective) decreases, due to reverse biasing effect of drain and the substrate.
when L(i.e the effective channel length) decreases Id increases.
Thus the drain current is controlled not only by the gate voltage, but also by the
drain voltage. threshold voltage reduction depending on the drain voltage.

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A slight increase in Id is visible and is more in short channel devices.
The modified equation is
For Lc=15nm
Vt drops too much, Ioff becomes too large and that channel length is not acceptable.

19
MOSFET Lab – Scaling
Tool Limitations
✓ Few bias points during the large bias sweep (Vg or Vd sweep) might lead to non
convergence.
✓ No poly depletion effects are included in the simulations.
✓ Quantum effects are not present in the simulations.
What is a SOI-MOSFET?
(Silicon on Insulator) metal–oxide–semiconductor field-effect transistor (SOI)
MOSFET: semiconductor device formed above an insulator
Advantages
✓ Better gate control over thinner channel
✓ Reduces short channel effects
Disadvantages
✓ Increases parasitic resistance
✓ Quantization effects come in leading to increasing (threshold voltage) Vt
Setting voltage sweeping for Id -Vg characteristics at low Vd =0.001 highVd=0.8

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For Lc =100 nm
DIBL= (0.126-.103)/(0.8-0.001)= 28.786mV/V
Threshold Voltage, Vt =~ 0.08V
Subthreshold slope, SS= (.05-0.01)/log(3.981e-5/1.469e-5) ~ 92.38 mV/dec
Ion/Ioff = Ids(at Vg=1.5Vd=.08)/ Ids(at Vg=0,Vd=.8)=4.24e-3/1.369e-5=0.31E+3
DIBL= 28.78mV/V
Vt =~ 0.0.08 V
SS ~92.38mV/dec
Ion/Ioff =0.312e3

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For Lc =75 nm
DIBL= high
Subthreshold slope, SS= (.0008-0.024)/log(3.226e-5/2.292e-5) ~ 107.78mV/dec
Ion/Ioff = Ids(at Vg=1.5Vd=.08)/ Ids(at Vg=0,Vd=.8)=4.24e-3/1.369e-5=0.31E+3
The potential fluctuations affect the magnitude of the current and the threshold
voltage for devices fabricated on a same chip.
For Lc =50 nm For Lc =30 nm
DIBL= high
Vt =~ 0.008 V
SS ~107.78mV/dec
Ion/Ioff =0.31e3

22
Double-Gate FET
In this device both the gates are placed in symmetry covering the channel which are
present at the opposite of each other. The channel is formed near the gate. In this
device both the gates are connected to the same potential and they have the same
dimensions so it is known as symmetric DG-FET
For Lc=100 nm
DIBL= 255.71
mV/V
Vt =~ 0.199 V
Ion/Ioff =33.177

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DIBL= -(0.22-0.399)/(0.8-0.1)= 255.71mV/V
Ion/Ioff = Ids(at Vg=3Vd=.08)/ Ids(at Vg=0,Vd=.8)=33.177
For Lc=75 nm
DIBL=high
Saturation and Leakage Currents: Ion = 5.6180E-03 and Ioff =0.1649e-3
Ion/Ioff = Ids(at Vg=3Vd=.08)/ Ids(at Vg=0,Vd=.8)=34.07
DIBL= high
Vt =~ 0.099 V
Ion/Ioff =34.07

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The potential fluctuations affect the magnitude of the current and the threshold
voltage for devices fabricated on a same chip.
Answers
Q1) As the head of the company you need to decide which process
technology (Bulk/UTB/DG) will be able to deliver the chip performance for
each year with minimum complexity. (You need to design for NMOS only).
Performance DIBL mv/v Ion/Ioff
Channel Length 100 75 50 30 15 100 75 50 30 15
Bulk MOSFET 66.66 66.6 133.3 High High 15.9e3 0.65e3 1.08e3 H H
SOI MOSFET 28.75 High High H H 0.31e3 0.31e3 High H H
DG-MOSFET 255.7 High H H H 33.17 34.07 High H H
Process Bulk
SOI
Bulk Bulk Use
less
Use
less
Bulk
SOI
Bulk Bulk no non

25
Q2) Do you have a solution for Year 5 (L=15nm). If you could scale SiO2
thickness till tox=0.2 nm can you still be competitive.
Oxide thickness’s influence on threshold voltage threshold voltage decreases with
scaling down of oxide thickness increase of leakage current Ioff
As threshold voltage(Vth) of a mosfet depends inversely on capacitance in oxide
layer (between gate and substrate)Cox , Cox=€ox/Tox
Since, Cox is itself reduces on increasing thickness of oxide layer (Tox)
Cox = Eox/Tox Eox = Er*Eo
Tox = thickness of oxide
Eo=Permittivity of free space 8.85E-14 F/um
Er=Permittivity of SiO2 3.9
Cox=gate oxide capacitance per unit area= 3.9*8.85E-18/0.2E-9=1.725E-3 F
When the gate voltage reaches a value called the threshold voltage (VT), the
substrate beneath the gate becomes inverted (it changes from p-type to n-type)
====================================================
Q3)
LG=45nm (each 15 nodes), oxide thickness of 1.2 nm (K=3.9, 5 nodes),poly-Si gate,
junction depth of 10 nm (20 nodes), and all other parameters at their nominal
preset values. change K to 20, and the oxide thickness to 6 nm, and resimulate the
device.

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Tox=1.2nm , k=3.9 Tox=1.2nm ,k=3.9
Leakage current Ioff=6.33E-5A saturation current Ion=0.00113A_ Vth =0.54 V
Tox=6nm , k=20 Tox=6nm , k=20
Leakage current Ioff=3.292E-5A saturation current Ion=0.0008A_ Vth =0.646 V

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